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DTSTAMP:20240626T180033Z
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DTSTART;TZID=America/Los_Angeles:20240626T163000
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UID:dac_DAC 2024_sess144_RESEARCH1609@linklings.com
SUMMARY:GNN-assisted Back-side Clock Routing Methodology for Advance Techn
 ologies
DESCRIPTION:Research Manuscript\n\nNesara Eranna Bethur and Pruek Vanna-ia
 mpikul (Georgia Institute of Technology); Odysseas Zografos (imec); Lingju
 n Zhu (Georgia Institute of Technology); Giuliano Sisto and Dragomir Miloj
 evic (imec); Alberto Garcia-Ortiz (University of Bremen); Geert Hellings, 
 Julien Ryckaert, and Francky Catthoor (imec); and Sung Kyu Lim (Georgia In
 stitute of Technology)\n\nThe back-side metal layers exhibit lower parasit
 ics compared to the front-side layers in advanced technologies, making the
 m suitable for clock-net distribution. In this study, we explore the advan
 tages of using back-side metal layers for clock routing, which is shared w
 ith a power delivery network. Our Graph Neural Network (GNN) based framewo
 rk, effectively distributes the clock-tree between the front and back side
 s. We address the back-side clock nets' creation by incorporating back-sid
 e buffers. Our results demonstrate better clock and full-chip metrics repr
 esented by an increase of up to 13% in the effective frequency with equiva
 lent power consumption, using 3 nm technology.\n\nTopic: EDA\n\nKeyword: P
 hysical Design and Verification\n\nSession Chairs: UDAY MALLAPPA (Intel Co
 rporation) and Satish Sivaswamy (Advanced Micro Devices (AMD))
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