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UID:dac_DAC 2024_sess144_RESEARCH1720@linklings.com
SUMMARY:DGR: Differentiable Global Router
DESCRIPTION:Research Manuscript\n\nWei Li (Carnegie Mellon University); Ro
 ngjian Liang, Anthony Agnesina, and Haoyu Yang (NVIDIA); Chia-Tung Ho (Uni
 versity of California, San Diego); and Anand Rajaram and Haoxing Ren (NVID
 IA)\n\nModern VLSI design flows necessitate fast and high-quality global r
 outers. In this paper, we introduce DGR, a GPU-accelerated, differentiable
  global router capable of concurrent optimization for millions of nets, wh
 ich we aim to open-source. Our innovation lies in the development of a rou
 ting Directed Acyclic Graph (DAG) forest to represent the 2D pattern routi
 ng space for all nets, enabling coordinated selection of Steiner trees and
  2-pin routing paths from a global perspective. For efficient search withi
 n the DAG forest, we relax the discrete search space to be continuous and 
 develop a differentiable solver accelerated by deep learning toolkits on G
 PUs. Experimental results demonstrate that DGR substantially mitigates rou
 ting overflow while concurrently reducing total wirelengths from 0.95% to 
 4.08% and via numbers from 1.28% to 2.54% in congested testcases compared 
 to state-of-the-art academic global routers. Additionally, DGR exhibits fa
 vorable scalability in both runtime and memory with respect to the number 
 of nets.\n\nTopic: EDA\n\nKeyword: Physical Design and Verification\n\nSes
 sion Chairs: UDAY MALLAPPA (Intel Corporation) and Satish Sivaswamy (Advan
 ced Micro Devices (AMD))
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