BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180034Z
LOCATION:3010\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240626T153000
DTEND;TZID=America/Los_Angeles:20240626T154500
UID:dac_DAC 2024_sess144_RESEARCH452@linklings.com
SUMMARY:Obstacle-Aware Length-Matching Routing for Any-Direction Traces in
  Printed Circuit Board
DESCRIPTION:Research Manuscript\n\nWeijie Fang, Longkun Guo, and Jiawei Li
 n (Fuzhou University); xiong silu (Huawei); Huan He (Hangzhou Huawei Enter
 prises Telecommunication Technologies Co., LTD); Jiacen Xu (Shanghai LEDA 
 Technology Co., Ltd); and Jianli Chen (Fudan University)\n\nEmerging appli
 cations in Printed Circuit Board (PCB) routing impose new challenges on au
 tomatic length matching, including adaptability for any-direction traces w
 ith their original routing preserved for interactiveness. The challenges c
 an be addressed through two orthogonal stages: assign non-overlapping rout
 ing regions to each trace and meander the traces within their regions to r
 each the target length. In this paper, mainly focusing on the meandering s
 tage, we propose an obstacle-aware detailed routing approach to optimize t
 he utilization of available space and achieve length matching while mainta
 ining the original routing of traces. Furthermore, our approach incorporat
 ing the proposed Multi-Scale Dynamic Time Warping (MSDTW) method can also 
 handle differential pairs against common decoupled problems. Experimental 
 results demonstrate that our approach has effective length-matching routin
 g ability and compares favorably to previous approaches under more complic
 ated constraints.\n\nTopic: EDA\n\nKeyword: Physical Design and Verificati
 on\n\nSession Chairs: UDAY MALLAPPA (Intel Corporation) and Satish Sivaswa
 my (Advanced Micro Devices (AMD))
END:VEVENT
END:VCALENDAR