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DTSTAMP:20240626T180034Z
LOCATION:3010\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240626T171500
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UID:dac_DAC 2024_sess144_RESEARCH502@linklings.com
SUMMARY:Concurrent Detailed Routing with Pin Pattern Re-generation for Ult
 imate Pin Access Optimization
DESCRIPTION:Research Manuscript\n\nYing-Jie Jiang and Shao-Yun Fang (Natio
 nal Taiwan University of Science and Technology)\n\nPin access has become 
 one of the most significant challenges in large-scale full-chip routing du
 e to the continuous reduction in feature sizes and the increasing complexi
 ty of designs. The conventional standard cell layout synthesis approaches 
 usually optimize pin accessibility by maximizing pin lengths and access po
 ints. However, these pre-determined pin patterns greatly occupy routing re
 sources and may contrarily degrade routability. To address this problem, t
 his paper proposes the first work of concurrent detailed routing with pin 
 pattern re-generation to achieve ultimate pin access optimization. A pseud
 o-pin extraction and routing technique is proposed that can secure one acc
 ess point for each input/output pin while allowing the remaining access po
 ints to be routable by other nets. The experimental results demonstrate th
 at the proposed method can resolve 89% of local regions that are unroutabl
 e with original layout patterns without compromising power and timing perf
 ormances.\n\nTopic: EDA\n\nKeyword: Physical Design and Verification\n\nSe
 ssion Chairs: UDAY MALLAPPA (Intel Corporation) and Satish Sivaswamy (Adva
 nced Micro Devices (AMD))
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