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DTSTAMP:20240626T180002Z
LOCATION:3008\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240627T133000
DTEND;TZID=America/Los_Angeles:20240627T153000
UID:dac_DAC 2024_sess150@linklings.com
SUMMARY:"Memory Is the Scribe of the Soul" Be It Volatile or Not
DESCRIPTION:Research Manuscript\n\nit is "still" the memory stupid! would 
 say R. Sites, main or secondary memory, or even non-volatile one. This ses
 sion presents 8 papers about unprecedented opportunities and challenges re
 lated to memory systems: 2 on DRAM/main memory optimization on technologic
 al or architectural aspects, 2 papers on prospective Non-Volatile Memory t
 echnologies (STT-RAM and RRAM) for enhancing energy consumption on embedde
 d systems, 2 papers on high performance emerging SSDs, one paper on ZRAM o
 ptimization for mobile systems and one on In-Memory computing for graphs.\
 n\nzeroTT: A Two-Step State Transition Avoidance Scheme for MLC STT-RAM\n\
 nCompared with conventional SRAM, Spin-Transfer Torque Random Access Memor
 y(STT-RAM) is expected to play a crucial role in future memory technologie
 s with the increasing demands for higher storage density and lower power c
 onsumption for modern embedded systems. Moreover, Multi-Level Cell (MLC) S
 TT-RA...\n\n\nDong Yin and Huizhang Luo (Hunan University); Jeff Zhang (Ar
 izona State University); and Mingxing Duan, Wangdong Yang, Zhuo Tang, and 
 Kenli Li (Hunan University)\n---------------------\nPipeSSD: A Lock-free P
 ipelined SSD Firmware Design for Multi-core Architecture\n\nModern SSD fir
 mware is continuously optimized for higher parallelism to match the growin
 g frontend PCIe bandwidth with more backend flash channels. Although a mul
 ti-core microprocessor is typically adopted to concurrently process indepe
 ndent NVMe requests from multiple NVMe queues, the existing one-...\n\n\nZ
 elin Du (The Chinese University of Hong Kong), Shaoqi Li (Shenzhen Univers
 ity), Zixuan Huang and Jin Xue (The Chinese University of Hong Kong), Tian
 yu Wang (Shenzhen University), and Kecheng Huang and Zili Shao (The Chines
 e University of Hong Kong)\n---------------------\nBalloon-ZNS: Constructi
 ng High-Capacity and Low-Cost ZNS SSDs with Built-in Compression\n\nThis p
 aper proposes Balloon-ZNS that enables transparent compression in emerging
  storage devices ZNS SSDs to enhance cost efficiency. ZNS SSDs require dat
 a pages to be stored and aligned in logical zones and flash blocks, confli
 cting with the management of variable-length compressed pages. Motivated..
 .\n\n\nYu Wang, Zibin Sun, and You Zhou (Huazhong University of Science an
 d Technology); Tao Lu (DapuStor Corporation); and Changsheng Xie and Fei W
 u (Huazhong University of Science and Technology)\n---------------------\n
 TAPMM:A Traffic-Aware Page Mapping Method for Multi-level NUMA Systems\n\n
 With the development of chiplet technology, the architecture of Non-Unifor
 m Memory Access (NUMA) has become increasingly intricate. The placement of
  memory page significantly influences application performance in NUMA syst
 ems. We found that memory access bottlenecks occur between high-level NUMA
  dom...\n\n\nFengkun Dong, Guoqing Xiao, Haotian Wang, Yikun Hu, Kenli Li,
  and Wangdong Yang (Hunan University)\n---------------------\nReducing DRA
 M Latency via In-situ Temperature- and Process-Variation-Aware Timing Dete
 ction and Adaption\n\nLong DRAM access latency has a significant impact on
  modern system performance. However, the improvement of access latency is 
 limited as the DRAM vendors reserve considerable timing margins against se
 ldom worst-case conditions. To mitigate such pessimistic timing margins, w
 e propose a temperature- a...\n\n\nYuxuan Qin and Chuxiong Lin (Shanghai J
 iao Tong University), Shi Xu (National Innovation Institute of Defense Tec
 hnology), Mingche Lai and Zhang Luo (National University of Defense Techno
 logy), and Weifeng He (Shanghai Jiao Tong University)\n-------------------
 --\nA RRAM-based High Energy-efficient Accelerator Supporting Multimodal T
 asks for Virtual Reality Wearable Devices\n\nVirtual reality (VR) wearable
  devices can achieve immersive entertainment by fusing multi-modal tasks f
 rom various senses. However, constrained by the short battery life and lim
 ited hardware resources of VR devices, it is difficult to run multiple tas
 ks simultaneously with different modals. Based on...\n\n\nXin ZHAO, Zhiche
 ng Hu, Zilong Guo, Haodong Fan, Xi Yang, Jing Zhou, and Liang Chang (Unive
 rsity of Electronic Science and Technology of China)\n--------------------
 -\nElasticZRAM: Revisiting ZRAM for Swapping on Mobile Devices\n\nModern m
 obile devices adopt two-level memory swapping consisting of ZRAM and stora
 ge devices to relieve memory pressure. \nIn the swap subsystem, ZRAM can i
 mprove application responsiveness and reduce write traffic to storage devi
 ces while consuming physical memory and additional CPU cycles.\nTo bette..
 .\n\n\nWentong Li, Dingcui Yu, Yunpeng Song, Longfei Luo, and Liang Shi (E
 ast China Normal University)\n---------------------\nA Combined Content Ad
 dressable Memory and In-Memory Processing Approach for k-Clique Counting A
 cceleration\n\nk-Clique counting problem plays an important role in graph 
 mining which has seen a growing number of applications. However, current k
 -Clique counting accelerators cannot meet the performance requirement main
 ly because they struggle with high data transfer issue incurred by the int
 ensive set intersec...\n\n\nXidi Ma, Weichen Zhang, and Xueyan Wang (Beiha
 ng University); Tianyang Yu and Bi Wu (Nanjing University of Aeronautics a
 nd Astronautics); Gang Qu (Univ. of Maryland, College Park); and Weisheng 
 Zhao (Beihang University)\n\nTopic: Embedded Systems\n\nKeyword: Embedded 
 Memory and Storage Systems\n\nSession Chair: Filippo Carloni (Politecnico 
 di Milano)
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