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DTSTAMP:20240626T180034Z
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DTSTART;TZID=America/Los_Angeles:20240627T140000
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UID:dac_DAC 2024_sess150_RESEARCH1159@linklings.com
SUMMARY:zeroTT: A Two-Step State Transition Avoidance Scheme for MLC STT-R
 AM
DESCRIPTION:Research Manuscript\n\nDong Yin and Huizhang Luo (Hunan Univer
 sity); Jeff Zhang (Arizona State University); and Mingxing Duan, Wangdong 
 Yang, Zhuo Tang, and Kenli Li (Hunan University)\n\nCompared with conventi
 onal SRAM, Spin-Transfer Torque Random Access Memory(STT-RAM) is expected 
 to play a crucial role in future memory technologies with the increasing d
 emands for higher storage density and lower power consumption for modern e
 mbedded systems. Moreover, Multi-Level Cell (MLC) STT-RAM outperforms Sing
 le-Level Cell (SLC) STT-RAM since it can store multiple bits per cell. How
 ever, MLC STT-RAM suffers from the occurrence of two-step state transition
 s (TTs) due to additional flipping of soft domains. Existing approaches mi
 tigate this problem by reducing TTs with data coding. However, none of the
 m can eliminate all the TTs. In this work, we propose a two-step transitio
 n avoidance scheme, referred to as zeroTT, for MLC STT-RAM. We show why th
 e existing (2,3)-based coding methods cannot avoid TTs. Then, we refine th
 e problem of expansion coding and present how to find zeroTT coding method
 s. Lastly, we propose an optimal (3,4)-based coding method considering the
  issues of space overhead and coding complexity. The experimental results 
 demonstrate that zeroTT can completely avoid TTs, leading to a more effici
 ent MLC STT-RAM in terms of latency, energy consumption, and lifetime.\n\n
 Topic: Embedded Systems\n\nKeyword: Embedded Memory and Storage Systems\n\
 nSession Chair: Filippo Carloni (Politecnico di Milano)
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