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DTSTAMP:20240626T180033Z
LOCATION:3008\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240627T141500
DTEND;TZID=America/Los_Angeles:20240627T143000
UID:dac_DAC 2024_sess150_RESEARCH238@linklings.com
SUMMARY:A RRAM-based High Energy-efficient Accelerator Supporting Multimod
 al Tasks for Virtual Reality Wearable Devices
DESCRIPTION:Research Manuscript\n\nXin ZHAO, Zhicheng Hu, Zilong Guo, Haod
 ong Fan, Xi Yang, Jing Zhou, and Liang Chang (University of Electronic Sci
 ence and Technology of China)\n\nVirtual reality (VR) wearable devices can
  achieve immersive entertainment by fusing multi-modal tasks from various 
 senses. However, constrained by the short battery life and limited hardwar
 e resources of VR devices, it is difficult to run multiple tasks simultane
 ously with different modals. Based on the above issues, we propose an ener
 gy-efficient accelerator that supports Multi-modal Tasks for VR devices, n
 amely MTVR. We present a multi-task computing solution based on the flexib
 le multi-task computing core design and efficient computing unit allocatio
 n strategy, which simultaneously achieves efficient work of multi-modal ta
 sks. We have designed an early exit detector to skip invalid calculations,
  which saves energy greatly. In addition, a fine-grained tiny value skip m
 ethod at multiplier and adder levels is proposed to save energy\nfurther. 
 We provide a hybrid RRAM and SRAM memory access scheme, reducing the exter
 nal memory access (EMA). Through experimental evaluation, the multi-task c
 omputing core achieves an average computational utilization of 95%. When t
 he invalid input ratio is 90%, energy saving brought by the early exit det
 ector can reach 88%. The tiny value skip method further achieved 13% energ
 y saving. A hybrid memory access scheme obtains a 98.9% EMA reduction. We 
 deployed the MTVR accelerator in FPGA and self-designed RRAM, achieving en
 ergy efficiency of 3.6 TOPS/W, higher than other single-task accelerators.
 \n\nTopic: Embedded Systems\n\nKeyword: Embedded Memory and Storage System
 s\n\nSession Chair: Filippo Carloni (Politecnico di Milano)
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