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DTSTART:19700308T020000
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DTSTAMP:20240626T180033Z
LOCATION:3012\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240625T113000
DTEND;TZID=America/Los_Angeles:20240625T114500
UID:dac_DAC 2024_sess152_RESEARCH1522@linklings.com
SUMMARY:HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural N
 etworks
DESCRIPTION:Research Manuscript\n\nWilfread Guillemé (INRIA), Angeliki Kr
 itikakou (Université de Rennes), Youri Helen (DGA MI), Cedric Killian (Uni
 versite Jean Monnet), and Daniel Chillet (Université de Rennes)\n\nEmbedde
 d Neural Networks (NNs) face significant challenges due to Single-Event Up
 sets (SEUs), compromising their reliability. To address this challenge, pr
 evious works study SEU layers sensitivity of AI models. Contrary to these 
 techniques, remaining at high level, we propose a more accurate analysis, 
 highlighting that, except for the last layer, faults transitioning from 0 
 to 1 significantly impact classification outcomes. Based on this specific 
 behavior, we propose a simple hardware block able to detect and mitigate t
 he SEU impact. Obtained results show that HTAG protection efficiency is ne
 ar 96.85% for the LeNet-5 CNN inference model, suitable for an embedded sy
 stem. This result can be improved with other protection methods for the cl
 assification layer. Additionally, it significantly reduces area overhead a
 nd critical path compared to existing approaches.\n\nTopic: Embedded Syste
 ms\n\nKeyword: Time-Critical and Fault-Tolerant System Design\n\nSession C
 hairs: Corey Tessler (University of Nevada, Las Vegas) and Chun-Feng Wu (N
 ational Yang Ming Chiao Tung University)
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