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DTSTAMP:20240626T180034Z
LOCATION:3012\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240625T104500
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UID:dac_DAC 2024_sess152_RESEARCH758@linklings.com
SUMMARY:A Cache/Algorithm Co-design for Parallel Real-Time Systems with Da
 ta Dependency on Multi/Many-core System-on-Chips
DESCRIPTION:Research Manuscript\n\nZhe Jiang (Southeast University), Shuai
  Zhao (Sun Yat-Sen University), Ran Wei (University of Cambridge), Yiyang 
 Gao (Sun Yat-Sen University), and Jing Li (New Jersey Institute of Technol
 ogy)\n\nParallel real-time systems often rely on the shared cache for depe
 ndent data transmissions across cores. Conventional shared cache and their
  management techniques suffer from intensive contention and are markedly i
 nflexible, leading to significant transmission latency of shared data. In 
 this paper, we provide a Virtual Indexed Physical Tagged, Selectively-Incl
 usive Non-Exclusive L1.5 Cache, offering way-level control and versatile s
 haring capabilities. Focusing on a common-seen parallel task model, the Di
 rected Acyclic Graph (DAG), we construct a novel scheduling method that ex
 ploits the L1.5 Cache to reduce data transmission latency, achieving impro
 ved timing performance. As a systematical solution, we build a real system
 , from the SoC and ISA to the drivers and the programming model. Experimen
 ts show that the proposed solution significantly improves the real-time pe
 rformance of DAG tasks with negligible hardware overhead.\n\nTopic: Embedd
 ed Systems\n\nKeyword: Time-Critical and Fault-Tolerant System Design\n\nS
 ession Chairs: Corey Tessler (University of Nevada, Las Vegas) and Chun-Fe
 ng Wu (National Yang Ming Chiao Tung University)
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