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DTSTAMP:20240626T180002Z
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DTSTART;TZID=America/Los_Angeles:20240626T153000
DTEND;TZID=America/Los_Angeles:20240626T173000
UID:dac_DAC 2024_sess154@linklings.com
SUMMARY:Hardware Security Primitives
DESCRIPTION:Research Manuscript\n\nThis session includes eight papers on t
 he latest development of hardware security primitives for security and pri
 vacy. The first paper describes a novel circuit architecture for true rand
 om number generation (TRNG).  The second paper proposes an authenticated p
 artial encryption protocol to enable secure testing of system in package (
 SiP). The third paper presents an architecture for the processing of multi
 -scalar multiplication, a fundamental cryptographic operation. Then we hav
 e a group of papers focusing on the acceleration of fully homomorphic encr
 yption (FHE) based on the low-level operator Meta-OP (paper No. 4); a scal
 able memory mapping algorithm and a flexible no-stall hardware/software pi
 peline (paper No. 5); specialized units for the pipelined processing of FH
 E operations (paper No. 6); and 3D stacked memory (paper No. 7). The sessi
 on concludes with the design and fabrication of a subthreshold SRAM PUF wi
 th zero bit error rate across all voltage/temperature corners.\n\nS2RAM PU
 F: An Ultra-low Power Subthreshold SRAM PUF with Zero Bit Error Rate\n\nTh
 e reliability of physical unclonable function (PUF) has become the biggest
  challenge for key generation. Existing reliability improvement technologi
 es incur high hardware overhead or testing costs. This paper proposes S2RA
 M-PUF, a novel, highly reliable and energy-efficient subthreshold SRAM PUF
  f...\n\n\nLi Ni and Jiliang Zhang (Hunan University)\n-------------------
 --\nGATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Pack
 age\n\nA heterogeneous integrated system in package (SIP) system integrate
 s chiplets outsourced from different vendors into the same substrate for b
 etter performance. However, during post-integration testing, the sensitive
  testing data designated for a specific chiplet can be blocked, tampered o
 r sniffed b...\n\n\nGALIB IBNE HAIDAR, Kimia Zamiri Azar, Hadi Mardani Kam
 ali, Mark Tehranipoor, and Farimah Farahmandi (University of Florida)\n---
 ------------------\nAn NTT/INTT Accelerator with Ultra-High Throughput and
  Area Efficiency for FHE\n\nAs a core arithmetic operation and security gu
 arantee of Fully Homomorphic Encryption (FHE), Number Theoretic Transform 
 (NTT) of a large degree is the primary source of computational and time ov
 erhead. In this paper, we propose a scalable and conflict-free memory mapp
 ing algorithm that breaks the me...\n\n\nZhaojun Lu, Weizong Yu, Peng Xu, 
 and Wei Wang (Huazhong University of Science and Technology); Jiliang Zhan
 g (Hunan University); and Dengguo Feng (State Key Laboratory of Cryptology
 )\n---------------------\nPPGNN: Fast and Accurate Privacy-Preserving Grap
 h Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic
  FHE Accelerator\n\nGraph Neural Networks (GNNs) are increasingly used in 
 fields like social media and bioinformatics, promoting the prosperity of c
 loud-based GNN inference services. Nevertheless, data privacy becomes a cr
 itical issue when handling sensitive information. Fully Homomorphic Encryp
 tion (FHE) enables compu...\n\n\nYuntao Wei, Xueyan Wang, Song Bian, Yiche
 ng Huang, and Weisheng Zhao (Beihang University) and Yier Jin (University 
 of Science and Technology in China)\n---------------------\nAlchemist: A U
 nified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encrypt
 ion\n\nThe use of cross-scheme fully homomorphic encryption (FHE) in priva
 cy-preserving applications challenges hardware accelerator design. Existin
 g accelerator architectures fail to efficiently handle hybrid FHE schemes 
 due to the mismatch between computational demands and hardware resources. 
 We propose ...\n\n\nJianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen L
 iu, and Shengwen Liang (Institute of Computing Technology, Chinese Academy
  of Sciences); Meng Li (Peking University); Mingzhe Zhang (Institute of In
 formation Engineering, Chinese Academy of Sciences); Song Bian (Beihang Un
 iversity); and Xing Hu, Huaiwei Li, and Xiaowei Li (Institute of Computing
  Technology, Chinese Academy of Sciences)\n---------------------\nA High-T
 hroughput Private Inference Engine Based on 3D Stacked Memory\n\nFully Hom
 omorphic Encryption (FHE) enables unlimited computation depth, allowing fo
 r privacy-enhanced neural network inference tasks directly on the cipherte
 xt. However, existing FHE architectures suffer from the memory access bott
 leneck due to the significant data consumption. This work proposes a ...\n
 \n\nZhaohui Chen (Alibaba Group); LING LIANG (Peking University); and Qi L
 iu, Zhirui Li, Fahong Zhang, Yanheng Lu, and Zhen Gu (Alibaba Group)\n----
 -----------------\nDH-TRNG: A Dynamic Hybrid TRNG with Ultra-High Throughp
 ut and Area-Energy Efficiency\n\nAs a vital security primitive, the true r
 andom number generator (TRNG) is a mandatory component to build roots of t
 rust for any encryption system. However, existing TRNGs suffer from bottle
 necks of low throughput and high area-energy consumption. In this work, we
  propose DH-TRNG, a dynamic hybrid TR...\n\n\nYuan Zhang, Kuncai Zhong, an
 d Jiliang Zhang (Hunan University)\n---------------------\nGypsophila: A S
 calable and Bandwidth-Optimized Multi-Scalar Multiplication Architecture\n
 \nMulti-Scalar Multiplication (MSM) is a fundamental cryptographic\nprimit
 ive, which plays a crucial role in Zero-knowledge proof systems.\nIn this 
 paper, we optimize the single MSM Process Element\n(PE) utilizing buckets 
 with fewer conflicts, enhanced by Greedy-based\nscheduling, to achieve hig
 her effici...\n\n\nChangxu Liu, Hao Zhou, Lan Yang, and Jiamin Xu (Fudan U
 niversity); Patrick Dai (Semisand Chip Design Pte.Ltd); and Fan Yang (Fuda
 n University)\n\nTopic: Security\n\nKeyword: Hardware Security: Primitives
 , Architecture, Design & Test\n\nSession Chair: Dean Sullivan (University 
 of New Hampshire)
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