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DTSTAMP:20240626T180034Z
LOCATION:3003\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240625T133000
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UID:dac_DAC 2024_sess158_RESEARCH1469@linklings.com
SUMMARY:CSTrans-OPU: An FPGA-based Overlay Processor with Full Compilation
  for Transformer Networks via Sparsity Exploration
DESCRIPTION:Research Manuscript\n\nYueyin Bai, Keqing Zhao, Yang Liu, Hong
 ji Wang, Hao Zhou, Xiaoxing Wu, Jun Yu, and Kun Wang (Fudan University)\n\
 nIn this work, we propose CSTrans-OPU, an FPGA-based overlay processor wit
 h full compilation for transformer networks via sparsity exploration. Spec
 ifically, we customize a multi-precision processing element (PE) array wit
 h DSP-packing for unified computation format with full resource utilizatio
 n. Additionally, the introduced sorting and computation mode selection mod
 ules make it possible to explore the token sparsity. Moreover, equipped wi
 th a user-friendly compiler, CSTrans-OPU enables model parsing, operation 
 fusion, model quantization, instruction generation and reordering directly
  from model files. To the best of our knowledge, our CSTrans-OPU is the fi
 rst overlay processor for transformer networks considering sparsity.\n\nTo
 pic: AI, Design\n\nKeyword: AI/ML Architecture Design\n\nSession Chair: Hy
 oukjun Kwon (University of California, Irvine)
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