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DTSTAMP:20240626T180002Z
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DTSTART;TZID=America/Los_Angeles:20240625T133000
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UID:dac_DAC 2024_sess168@linklings.com
SUMMARY:Advanced Logic Synthesis - Improving Runtime and Quality
DESCRIPTION:Research Manuscript\n\nThis session includes six advanced logi
 c synthesis works in addressing fundamental challenges of runtime efficien
 cy and handling complex optimization objectives. The first two papers focu
 s on high-performance parallel DAG-aware logic synthesis, exploring both G
 PU and CPU parallelism. The third and fourth presentations introduce and m
 erge synthesis techniques in circuit-level architecture optimization, show
 casing parallel prefix circuit design and pipelining. The fifth and sixth 
 papers present novel formal methods, including Satisfiability and e-graphs
 , based on logic synthesis approaches to tackle complex optimization objec
 tives in the conventional logic synthesis process.\n\nSize-Optimized Depth
 -Constrained Large Parallel Prefix Circuits\n\nBinary adders are a critica
 l building block in integrated circuit (IC) design. In addition to the wid
 ely used 32/64/128-bit adders, large (1024/2048 bits) adders are important
  in applications such as cryptography. However, most current adder design 
 methods target regular bitwidths, and cannot effici...\n\n\nShiju Lin (The
  Chinese University of Hong Kong), Bentian Jiang and Weihua Sheng (Huawei)
 , and Evangeline Young (The Chinese University of Hong Kong)\n------------
 ---------\nE-Syn: E-Graph Rewriting with Technology-Aware Cost Functions f
 or Logic Synthesis\n\nLogic synthesis plays a crucial role in the digital 
 design flow. It has a decisive influence on the final Quality of Results (
 QoR) of the circuit implementations. However, existing multi-level logic o
 ptimization algorithms often employ greedy approaches with a series of loc
 al optimization steps. Eac...\n\n\nChen Chen and Guangyu Hu (Hong Kong Uni
 versity of Science and Technology (HKUST)); Dongsheng Zuo (The Hong Kong U
 niversity of Science and Technology (Guangzhou)); Cunxi Yu (University of 
 Maryland, College Park); Yuzhe Ma (The Hong Kong University of Science and
  Technology (Guangzhou)); and Hongce Zhang (Hong Kong University of Scienc
 e and Technology (HKUST))\n---------------------\nMassively Parallel AIG R
 esubstitution\n\nResubstitution is a flexible algorithmic framework for ci
 rcuit restructuring that has been incorporated into many high-effort logic
  optimization flows. It is thus important to speed up resubstitution in or
 der to obtain high-quality realizations of large-scale designs. This paper
  proposes a massively...\n\n\nYang Sun, Tianji Liu, Martin Wong, and Evang
 eline Young (The Chinese University of Hong Kong)\n---------------------\n
 DACPara: A Divide-and-Conquer Parallel Approach for High-Quality Logic Rew
 riting in Large-Scale Circuits\n\nLogic rewriting is a critical and time-c
 onsuming task in logic synthesis, which determines the area and delay of t
 he synthesized circuit. However, existing parallel solutions for this task
  suffer from limitations in terms of runtime or quality in large-scale com
 plex circuits. In this paper, we propo...\n\n\nNanjiang Qu, Cong Tian, and
  Zhenhua Duan (Xidian University)\n---------------------\nPONO: Power Opti
 mization with Near Optimal SMT-based Sub-circuit Generation\n\nGenerating 
 high-quality sub-circuit for local substitution is an effective optimizati
 on technique in logic synthesis. There have been abundant works on generat
 ing area and delay optimal sub-circuits, greatly enhancing the logic optim
 ization quality. However, power- oriented sub-circuit generation is...\n\n
 \nSunan Zou and Guojie Luo (Peking University)\n---------------------\nRev
 isiting Automatic Pipelining: Gate-level Forwarding and Speculation\n\nThe
  key to pipeline throughput optimization is to resolve data hazards caused
  by read-after-write (RAW) dependencies, which are traditionally tackled b
 y forwarding and speculation to avoid pipeline stalls. However,  existing 
 approaches are conducted based on high-level dataflow analysis, with poten
 t...\n\n\nShuyao Cheng, Chongxiao Li, Zidong Du, Rui Zhang, Xing Hu, Xiaqi
 ng Li, Guanglin Xu, Yuanbo Wen, and Qi Guo (Institute of Computing Technol
 ogy, Chinese Academy of Sciences)\n\nTopic: EDA\n\nKeyword: RTL/Logic Leve
 l and High-level Synthesis\n\nSession Chairs: Giovanni De Micheli (EPFL) a
 nd Cunxi Yu (University of Maryland)
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