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DTSTAMP:20240626T180033Z
LOCATION:3004\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240625T144500
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UID:dac_DAC 2024_sess168_RESEARCH252@linklings.com
SUMMARY:PONO: Power Optimization with Near Optimal SMT-based Sub-circuit G
 eneration
DESCRIPTION:Research Manuscript\n\nSunan Zou and Guojie Luo (Peking Univer
 sity)\n\nGenerating high-quality sub-circuit for local substitution is an 
 effective optimization technique in logic synthesis. There have been abund
 ant works on generating area and delay optimal sub-circuits, greatly enhan
 cing the logic optimization quality. However, power- oriented sub-circuit 
 generation is rarely discussed, while optimizing power consumption in this
  sub-15 nm era is of paramount interest. We propose PONO, an SMT-based nea
 r optimal sub-circuit generation flow for power optimization. PONO enables
  power-oriented circuit library building and fills the gap in generating c
 ircuits near the Pareto frontier in PPA (Power, Performance, and Area). It
  manifests superiority in power reduction over traditional one in rewrite,
  a key logic optimization algorithm. We test PONO on EFPL benchmarks, and 
 it shows 8.7% less power consumption with comparable performance and area 
 after placement and routing.\n\nTopic: EDA\n\nKeyword: RTL/Logic Level and
  High-level Synthesis\n\nSession Chairs: Giovanni De Micheli (EPFL) and Cu
 nxi Yu (University of Maryland)
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