BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180035Z
LOCATION:3004\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240625T141500
DTEND;TZID=America/Los_Angeles:20240625T143000
UID:dac_DAC 2024_sess168_RESEARCH311@linklings.com
SUMMARY:Revisiting Automatic Pipelining: Gate-level Forwarding and Specula
 tion
DESCRIPTION:Research Manuscript\n\nShuyao Cheng, Chongxiao Li, Zidong Du, 
 Rui Zhang, Xing Hu, Xiaqing Li, Guanglin Xu, Yuanbo Wen, and Qi Guo (Insti
 tute of Computing Technology, Chinese Academy of Sciences)\n\nThe key to p
 ipeline throughput optimization is to resolve data hazards caused by read-
 after-write (RAW) dependencies, which are traditionally tackled by forward
 ing and speculation to avoid pipeline stalls. However,  existing approache
 s are conducted based on high-level dataflow analysis, with potential loss
  of optimization opportunities for lack of analysis of the netlist structu
 res.\n\nWe propose an efficient method to resolve RAW dependencies with lo
 w-level netlist analysis by gate-level forwarding and speculation. With a 
 greedy search method to detect and resolve short-delay gate-level signal p
 aths for forwarding and an approximate circuit synthesis method with forma
 l verification for gate-level speculation, the method efficiently utilizes
  the gate-level information to further improve pipeline throughput. We con
 duct experiments on the widely-used ISCAS/EPFL benchmark circuits and a la
 rge-scale RISC-V CPU. Experimental results show that our approach can incr
 ease the pipeline throughput. More importantly, our approach can find bett
 er designs than human experts.\n\nTopic: EDA\n\nKeyword: RTL/Logic Level a
 nd High-level Synthesis\n\nSession Chairs: Giovanni De Micheli (EPFL) and 
 Cunxi Yu (University of Maryland)
END:VEVENT
END:VCALENDAR