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UID:dac_DAC 2024_sess168_RESEARCH655@linklings.com
SUMMARY:E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for 
 Logic Synthesis
DESCRIPTION:Research Manuscript\n\nChen Chen and Guangyu Hu (Hong Kong Uni
 versity of Science and Technology (HKUST)); Dongsheng Zuo (The Hong Kong U
 niversity of Science and Technology (Guangzhou)); Cunxi Yu (University of 
 Maryland, College Park); Yuzhe Ma (The Hong Kong University of Science and
  Technology (Guangzhou)); and Hongce Zhang (Hong Kong University of Scienc
 e and Technology (HKUST))\n\nLogic synthesis plays a crucial role in the d
 igital design flow. It has a decisive influence on the final Quality of Re
 sults (QoR) of the circuit implementations. However, existing multi-level 
 logic optimization algorithms often employ greedy approaches with a series
  of local optimization steps. Each step breaks the circuit into small piec
 es (e.g., k-feasible cuts) and applies incremental changes to individual p
 ieces separately. These local optimization steps could limit the explorati
 on space and may miss opportunities for significant improvements. To addre
 ss the limitation, this paper proposes using e-graph in logic synthesis. T
 he new workflow, named E-Syn, makes use of the well-established e-graph in
 frastructure to efficiently perform logic rewriting. It explores a diverse
  set of equivalent Boolean representations while allowing technology-aware
  cost functions to better support delay-oriented and area-oriented logic s
 ynthesis. Experiments over a wide range of benchmark designs show our prop
 osed logic optimization approach reaches a wider design space compared to 
 the commonly used AIG-based logic synthesis flow. It achieves on average 1
 5.29% delay saving in delay-oriented synthesis and 6.42% area saving for a
 rea-oriented synthesis.\n\nTopic: EDA\n\nKeyword: RTL/Logic Level and High
 -level Synthesis\n\nSession Chairs: Giovanni De Micheli (EPFL) and Cunxi Y
 u (University of Maryland)
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