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DTSTAMP:20240626T180033Z
LOCATION:3004\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240625T140000
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UID:dac_DAC 2024_sess168_RESEARCH966@linklings.com
SUMMARY:Size-Optimized Depth-Constrained Large Parallel Prefix Circuits
DESCRIPTION:Research Manuscript\n\nShiju Lin (The Chinese University of Ho
 ng Kong), Bentian Jiang and Weihua Sheng (Huawei), and Evangeline Young (T
 he Chinese University of Hong Kong)\n\nBinary adders are a critical buildi
 ng block in integrated circuit (IC) design. In addition to the widely used
  32/64/128-bit adders, large (1024/2048 bits) adders are important in appl
 ications such as cryptography. However, most current adder design methods 
 target regular bitwidths, and cannot efficiently generate large adders wit
 h good performance. In practice, adders are often integrated into circuits
  such as a multiplier-accumulator (MAC), resulting in complex non-uniform 
 input arrival times. To address these challenges, we propose a new algorit
 hm for efficiently generating high-quality adders for non-uniform input ar
 rival times. It is based on a novel divide-and-conquer-friendly problem fo
 rmulation, and can effectively generate and maintain the most useful adder
  structures through dynamic programming.\nExperimental results show that i
 t outperforms the current state-of-the-art methods in both quality and run
 time. The adders generated by our algorithm have 2.8%, 8.3%, and 10.3% red
 uctions in delay, area, and power, respectively, compared to those generat
 ed by a commercial synthesis tool.\n\nTopic: EDA\n\nKeyword: RTL/Logic Lev
 el and High-level Synthesis\n\nSession Chairs: Giovanni De Micheli (EPFL) 
 and Cunxi Yu (University of Maryland)
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