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DTSTAMP:20240626T180033Z
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UID:dac_DAC 2024_sess169_RESEARCH1116@linklings.com
SUMMARY:High-Performance and Resource-Efficient Dynamic Memory Management 
 in High-Level Synthesis
DESCRIPTION:Research Manuscript\n\nQinggang Wang, Long Zheng, Zhaozeng An,
  Haoqin Huang, Haoran Zhu, Yu Huang, Pengcheng Yao, Xiaofei Liao, and Hai 
 Jin (Huazhong University of Science and Technology)\n\nThe usability and p
 opularity of high-level synthesis (HLS) tools are still limited due to lac
 k of support for dynamic memory management (DMM). Though HLS-compatible DM
 M solutions have been proposed recently, nevertheless, based on our invest
 igation, none of them can hit high performance (i.e., minimal memory (de-)
 allocation latency) and resource efficiency (i.e., managing arbitrarily si
 zed memory with minimal FPGA resource consumption) with one stone, serious
 ly limiting their practicality. In response, we propose HeroDMM, a high-pe
 rformance and resource-efficient dynamic memory manager for HLS. Results s
 how that HeroDMM outperforms state-of-the-art HLS-compatible DMM solutions
  by 61.69%--99.99% in performance improvement and 23.79%--97.22% in resour
 ce consumption savings.\n\nTopic: EDA\n\nKeyword: RTL/Logic Level and High
 -level Synthesis\n\nSession Chairs: Alexandros Papakonstantinou (Lemurian 
 Labs) and Evangeline Young (The Chinese University of Hong Kong)
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