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DTSTAMP:20240626T180033Z
LOCATION:3010\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240625T144500
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UID:dac_DAC 2024_sess169_RESEARCH733@linklings.com
SUMMARY:Knowing The Spec to Explore The Design via Transformed Bayesian Op
 timization
DESCRIPTION:Research Manuscript\n\nDonger Luo (Shanghai Tech University), 
 QI SUN (Zhejiang University), Xinheng Li (Shanghai Tech University), Chen 
 BAI and Bei Yu (The Chinese University of Hong Kong), and Hao Geng (Shangh
 ai Tech University)\n\nAI chip scales expediently in the large language mo
 dels (LLMs) era. In contrast, the existing chip design space exploration m
 ethods, aimed at discovering optimal yet often infeasible or unproduceable
  Pareto-front designs, are hindered by neglect of design specifications. I
 n this paper, we propose a novel Spec-driven transformed Bayesian optimiza
 tion framework to find expected optimal RISC-V SoC architecture designs fo
 r LLM tasks. The highlights of our framework lie in a tailored transformed
  Gaussian process (GP) model prioritizing specified target metrics and a c
 ustomized acquisition function (EHRM) in multi-objective optimization. Ext
 ensive experiments on large-scale RISC-V SoC architecture design explorati
 ons for LLMs, such as Transformer, BERT, and GPT-1, demonstrate that our m
 ethod not only can effectively find the design according to QoR values fro
 m the spec, but also outperforms 34.59% in ADRS over previous state-of-the
 -art approach with 66.67% runtime.\n\nTopic: EDA\n\nKeyword: RTL/Logic Lev
 el and High-level Synthesis\n\nSession Chairs: Alexandros Papakonstantinou
  (Lemurian Labs) and Evangeline Young (The Chinese University of Hong Kong
 )
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