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DTSTAMP:20240626T180033Z
LOCATION:3014\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240625T153000
DTEND;TZID=America/Los_Angeles:20240625T173000
UID:dac_DAC 2024_sess175_PANEL005@linklings.com
SUMMARY:Generative AI for Chip Design: Game Changer or Damp Squib?
DESCRIPTION:Research Panel\n\nSiddharth Garg (New York University); Ruchir
  Puri (IBM); Vidya A. Chhabria (Arizona State University); Amir Yazdanbakh
 sh (Google); Erik Berg (Microsoft); Stelois Diamantidis (Synopsys); Yong L
 iu (Cadence Design Systems, Inc.); and Subhashish Mitra (Stanford Universi
 ty)\n\nGenerative AI (GenAI) technologies for modalities including text, i
 mage, speech etc., are poised for huge practical impact in a range of indu
 stries. How will GenAI impact the EDA business, and perhaps conversely, do
 es EDA have a role to play in advancing GenAI?  Recent results suggest Gen
 AI can indeed play a transformative role across the design flow from chip 
 specification and verification, to pre- and post-silicon test, physical de
 sign and design for manufacturability, thereby improving designer producti
 vity, time-to-market and design quality. Conversely, EDA can play a crucia
 l role in addressing the massive training and inference costs of state-of-
 art trillion parameter or more GenAI models via pruning, specialization an
 d acceleration. The panel will seek to address several key questions the a
 bout the role of GenAI and EDA namely:\n\n(1) Can GenAI design a full chip
 ? Intentionally provocative, panelists will be asked whether GenAI methods
  alone, or with limited supervision, can translate natural language design
  intent to high-quality GDSII, along with test and verification procedures
 ? What role will human expertise, experience and intuition play in a GenAI
  driven flow, and which parts can be truly automated? In sum, what are the
  killer applications for GenAI in chip design?\n\n(2) Specialized vs. gene
 ral-purpose foundation models for chip design? Generalized foundation mode
 ls like GPT-4, Bard etc. have shown exceptional abilities to generalize to
  unseen tasks, including potentially RTL code and EDA script generation. W
 ill these massive foundation models suffice or do we need smaller and spec
 ialized foundation models for hardware design? Specialized models can impr
 ove performance on hardware=-specific tasks, in addition to having managea
 ble training and inference costs.\n\n(3) Open- vs. closed-sourced datasets
  and models for hardware? Many semiconductor companies have massive intern
 al datasets that can be used to train foundation models for hardware, but 
 these models will likely not  be released publicly due to IP issues. Unlik
 e for software, open datasets of hardware are scarce—for example, Verilog 
 is only 0.004% of the code on GitHub. Are there avenues for training large
  open-source GenAI models for chip design, or do we expect these models to
  be internal and/or black-boxed?\n\n(4) Regulatory, legal, safety and robu
 stness issues? The recent Executive Order by the Biden administration requ
 ires, amongst other things, the development of " standards, tools, and tes
 ts to help ensure that AI systems are safe, secure, and trustworthy." What
  does this mean for GenAI models in the EDA context? Models trained on ope
 n-source datasets must additionally worry about copyright and IP violation
  issues, user privacy and the ``right to be forgotten" and additional conc
 erns about inadvertent or malicious backdoors in ML models.\n\nTopic: AI, 
 EDA
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