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DTSTART:19700308T020000
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DTSTAMP:20240626T180033Z
LOCATION:3006\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20240626T140000
DTEND;TZID=America/Los_Angeles:20240626T143000
UID:dac_DAC 2024_sess182_SPSSN120@linklings.com
SUMMARY:Invited: HDL-GPT: High Quality HDL Is All You Need
DESCRIPTION:Special Session (Research)\n\nGanapathy Parthasarathy (Synopsy
 s)\n\nThis talk presents Hardware Description Language Generative Pre-Trai
 ned Transformers (HDL-GPT), a novel approach that leverages the vast repos
 itory of open-source Hardware Description Language (HDL) codes to train su
 perior quality large code models. The core premise of this research is the
  hypothesis that high-quality HDL is all you need to create models with ex
 ceptional performance and broad zero-shot generalization abilities. The ta
 lk elucidates the methods employed for the curation and augmentation of la
 rge corpora from open-source HDL code, transforming a highly variable qual
 ity data into high-quality data through careful prompting and context main
 tenance. We observe that the careful selection, filtering, and augmentatio
 n of data across HDLs can yield powerful models that surpass current state
 -of-the-art models. We also explore the impact of different fine-tuning me
 thods on quality of results. We analyzed and performed experiments across 
 a range of fine-tuned state-of-the-art LLMs. We demonstrate improvements o
 f 50% to 200% over state-of-the-art HDL models on current benchmarks in ta
 sks ranging from HDL circuit explanations, code generation, formal and sim
 ulation testbench creation, bug finding and fixing, to tasks in high-speed
  circuit design. HDLGPT opens new avenues for the development of advanced 
 model training techniques for circuit design tasks.\n\nTopic: AI\n\nSessio
 n Chair: Cong (Callie) Hao (Georgia Institute of Technology)
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