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DTSTART:19700308T020000
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DTSTAMP:20240626T180034Z
LOCATION:2008\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240624T144500
DTEND;TZID=America/Los_Angeles:20240624T150000
UID:dac_DAC 2024_sess184_BED082@linklings.com
SUMMARY:High Confidence Hierarchical bottom-up DVD methodology for EMIR Si
 gnoff of Automotive SOCs
DESCRIPTION:Back-End Design\n\nLove Gupta (NXP Semiconductors) and Manmeet
  Singh and Koshy John (Ansys)\n\nLatest Design trends with advanced techno
 logy nodes have resulted in shrinking of Dynamic Voltage Drop margins. Tra
 ditionally in the ASIC design cycle, PDN signoff is executed after full ch
 ip integration is finalised. This makes design susceptible to potential un
 warranted dynamic noise issues arising out of SOC integration and thereby 
 presenting crucial challenges to any last minute surprises for Power Integ
 rity closure. \n\nThis necessitates the requirement of a robust hierarchic
 al dvd methodology which promises high confidence of real impact dvd viola
 tions at block level, less surprises in new IR violations moving to top, a
 nd also ensuring faster convergence cycles when running a full chip transi
 ent analysis. \n\nIn this paper, we present an accurate and efficient hier
 archical dvd methodology which leverages use of smart load modelling and E
 vent Replay technology on Ansys RedHawk SC platform. With this approach, 2
 0% efficiency improvement has been observed in TAT and corelation of DVD V
 iolations has been observed which otherwise was leading to ~25% extra DVD 
 violations at SOC level.\n\nTopic: Back-End Design, Design, Engineering Tr
 acks\n\nSession Chair: Patricia Fong (Marvell Semiconductor)
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