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DTSTAMP:20240626T180033Z
LOCATION:2008\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240625T110600
DTEND;TZID=America/Los_Angeles:20240625T112400
UID:dac_DAC 2024_sess185_BED110@linklings.com
SUMMARY:Timing Robustness: A Way forward for analyzing timing-voltage sens
 itive paths for accounting IR-Drop Variations
DESCRIPTION:Back-End Design\n\nShourya Shukla, Lavanya Padmanabhuni, and S
 ainarayanan Suryanarayanan (Marvell) and Harshit Jaiswal, Sharath AC, and 
 Nitin Jain (Cadence Design Systems, Inc.)\n\nWith increasing grid resistan
 ce, modelling the impact of voltage drop on instances has been a focus of 
 research to improve timing robustness or yield. Furthermore, as technology
  node shrinks, RC constant is dominated by Resistance, with R increasing 1
 0x from 28nm-7nm, and cell delays are non-linear with IR drop, accounting 
 for higher delay variations at below nominal voltage domain.\nTraditionall
 y and still mostly as well, designers use derating techniques to account f
 or the IR drop. The limitation of this approach is that it is a flat OCV f
 actor and sometimes we penalize paths which are not as prone to voltage se
 nsitivity causing excessive pessimism and on the other hand could mask pot
 ential real violations. These issues paved the way towards IR aware STA wh
 erein voltage drop obtained from IR tools are back-annotated onto the timi
 ng engine. This method is robust but still depends on the coverage done us
 ing vectorless dynamic analysis. In order to perform analysis on timing cr
 itical and voltage sensitive path we need to have both the timer and the p
 ower-grid solver integrated so that we could perform more voltage sensitiv
 e focused critical timing path analysis. This methodology can serve as an 
 augmentation to regular signoff and can potentially unravel timing voltage
  sensitive instances which are missed by traditional methods leading to mo
 re robustness and silicon success. In this paper we will be presenting a c
 ase study on evolution and adoption for accounting IR-Drop variations, res
 ults and current limitations.\n\n  •  Timing-Power Integrated Flow for con
 current Timing and Voltage-Drop analysis: Paper will walk \n      through 
 the STA-PI integration flow with different STA and IR analysis corners und
 er a common \n      cockpit (SLOW corner STA and TYP corner IR) and evalua
 tes the benefits of timing-aware IR and \n      IR aware timing analysis\n
 \n  •  Detailed analysis on Timing/IR critical Block: Paper presents the q
 uantitative analysis done on \n      timing sensitive paths with annotated
  EIV values for voltage drop on timing instances and its \n      compariso
 n with the traditional Flat Voltage derates and IR-aware STA flow\n\n  •  
 Resource and runtime evaluation for Large Designs: With analysis done on a
  100M instance \n      block, paper will focus on the resource/runtime tra
 de-offs with PPA and robustness gains\n\n  •  Timing ECOs with EIV annotat
 ion and timing fixes: Timing ECOs with EIV annotated timing paths \n      
 with focus on fixing Voltage-Sensitive timing critical paths\n\n  •  Poten
 tial missed violations: Paper will also focus on timing paths which were n
 ot violating with Flat \n      voltage derates but seen as potential viola
 tors with the discussed flow\n\nTopic: Back-End Design, Design, Engineerin
 g Tracks\n\nSession Chair: Amol Joshi (Intel Corporation)
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