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DTSTAMP:20240626T180002Z
LOCATION:2008\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T103000
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UID:dac_DAC 2024_sess186@linklings.com
SUMMARY:Electron Signatures for Predicting the Diagnosis!
DESCRIPTION:Back-End Design\n\nEnhance your work to identify the signature
 s underlying high bandwidth interfaces, chip package board co-design or ju
 st closing optical and silicon robustness from leaking secrets to the outs
 ide world.\n\nPre-Silicon Photon Emission Modeling and Optical Side-Channe
 l Simulation\n\nOptical side-channel analysis poses a significant threat t
 o the security of integrated circuits (ICs) by enabling the disclosure of 
 secret data, such as encryption keys. In our work, we present a multiphysi
 cs simulation framework of optical side-channel analysis from the layout d
 atabase of a fabrica...\n\n\nHenian Li (University of Florida); Lang Lin, 
 Norman Chang, and Sreeja Chowdhury (Ansys); Kazuki Monta and Makoto Nagata
  (Kobe University); and Mark Tehranipoor (University of Florida)\n--------
 -------------\nUCIe-A 32GT/s power distributed network design-optimization
  at organic interposer with localized integrated passive decoupling capaci
 tors\n\nThis paper presents a power distributed networks (PDNs) design for
  UCIe-A (UCIe advanced package), at organic interposer technology. To meet
  UCIe-A power integrity requirement for voltage fluctuation (Vpp) less tha
 n 30mV, interposer level decoupling capacitors is a critical design (e.g.,
  distributed...\n\n\nSheng-Fan Yang (Global Unichip Corporation)\n--------
 -------------\nDie, Package and PCB Co-design for Low Area, High Signal to
  Power Pin Ratio in High Frequency SOC designs\n\nØ        Microcontroller
  designs are going through optimizations on multiple-scales to win market 
 share – be it performance, MIPS, feature-set, more peripheral access, more
  systems on chip supporting more applications.\n\nØ        Simultaneous su
 pport of varied applications and win customers man...\n\n\nKarthik Kodakan
 dla, Jakeerali Shaik, and MuraliMohan Thota (Texas Instruments (India) Pvt
 . Ltd.)\n---------------------\nSystem Aware IO Integrity Signoff\n\nIO in
 tegrity analysis early in the design cycle helps disintegrate the system l
 evel constraints from DIE level constraint. Integrity challenges are more 
 predominant with 324-529 BALL packages, in automotive infotainment SOCs wi
 th close to 200-400 signals including GHz DDR, EMAC, eMMC, xSPI etc. Tota.
 ..\n\n\nAnubhav Johri and Bijaya Dash (Analog Devices, Inc. (ADI))\n------
 ---------------\nSi Backside Side-Channel Leakage and Simulation of Crypto
 graphic IC Chips\n\nFlip chip mounting has been widely used in recent year
 s. Flip chip mounting has advantages such as shorter signal wires, smaller
  footprint, and multiple chip(lets).\n However, flip chip packaging makes 
 Si substrate as an attack surface, and then Si substrate voltage becomes o
 ne of the side-channel in...\n\n\nRikuu Hasegawa, Kazuki Monta, Takuya Wad
 atsumi, Takuji Miki, and Makoto Nagata (Kobe University) and Lang Lin, Sre
 eja Chowdhury, Akhilesh Kumar, and Norman Chang (Ansys)\n\nTopic: Back-End
  Design, Design, Engineering Tracks\n\nSession Chair: Badhri Uppiliappan (
 Analog Devices, Inc. (ADI))
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