BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:2008\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T103000
DTEND;TZID=America/Los_Angeles:20240626T104800
UID:dac_DAC 2024_sess186_BED028@linklings.com
SUMMARY:UCIe-A 32GT/s power distributed network design-optimization at org
 anic interposer with localized integrated passive decoupling capacitors
DESCRIPTION:Back-End Design\n\nSheng-Fan Yang (Global Unichip Corporation)
 \n\nThis paper presents a power distributed networks (PDNs) design for UCI
 e-A (UCIe advanced package), at organic interposer technology. To meet UCI
 e-A power integrity requirement for voltage fluctuation (Vpp) less than 30
 mV, interposer level decoupling capacitors is a critical design (e.g., dis
 tributed eDTC at CoWoS-S). However, at organic inteposer, it is still limi
 ted solution for localized and efficiently noises decoupling, especially, 
 UCIe-A X64E bump map IP hardmarco is with small dimension as 1225μm x 388.
 8μm.\nThis work proposes a localized decoupling capacitor integrated solut
 ion, deploying C4-bump-side integrated passive components (IPDs) at UCIe-A
  X64E die-to-die gap, which provides efficiently local decoupling paths fo
 r each UCIe-A IP macro, as well as without penalty of PDNs parasitics degr
 aded or occupied extra region for decoupling capacitors. \nThis work demon
 strates the design of UCIe-A X64E testchip in tsmc 3nm technology (tape ou
 t on 2023/Nov.), as well as interconnects and PDNs at tsmc 65nm organic in
 terposer (CoWoS-R, 8-RDL), where the PDNs co-simulated peak impedance (ZPD
 N) can be suppressed by 55% (from 21.59mΩ to 11.87mΩ, at 100MHz), as well 
 as peak-to-peak voltage fluctuation (Vpp) can be suppressed by 78.7% (from
  103.00mV to 21.98mV). With the good PDNs design, related power-aware SI c
 o-simulated eyediagram can achieve 0.78UI at 32GT/s.\n\nTopic: Back-End De
 sign, Design, Engineering Tracks\n\nSession Chair: Badhri Uppiliappan (Ana
 log Devices, Inc. (ADI))
END:VEVENT
END:VCALENDAR