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DTSTART:19700308T020000
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DTSTAMP:20240626T180034Z
LOCATION:2008\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T104800
DTEND;TZID=America/Los_Angeles:20240626T110600
UID:dac_DAC 2024_sess186_BED065@linklings.com
SUMMARY:Die, Package and PCB Co-design for Low Area, High Signal to Power 
 Pin Ratio in High Frequency SOC designs
DESCRIPTION:Back-End Design\n\nKarthik Kodakandla, Jakeerali Shaik, and Mu
 raliMohan Thota (Texas Instruments (India) Pvt. Ltd.)\n\nØ        Microcon
 troller designs are going through optimizations on multiple-scales to win 
 market share – be it performance, MIPS, feature-set, more peripheral acces
 s, more systems on chip supporting more applications.\n\nØ        Simultan
 eous support of varied applications and win customers mandate availability
  of higher count of pins/GPIOs as compared to predecessors/competitors – w
 hich indirectly means sacrificing the count of power/ground pins.\n\nØ    
     For our design, we have set target of power-pins reduction by 40% on C
 ore and IO power supplies, thereby providing more pins for GPIOs. Along wi
 th this, there was increase in supply tolerance.\n\nØ        Reduced count
  of power/ground pins, increased functionality, higher supply tolerance on
  IO supply have negative impacts on IR drop, timing, Signal Integrity (SI)
 , and hence overall design performance.\n\nØ        Industrial solutions l
 ike PTV compensation circuits, programmable drive cells would solve the pr
 oblem for SI, however, they bring higher area overhead.\n\nØ        Throug
 h this paper we present cost-effective (area) design strategies that were 
 incorporated to keep all the above design vectors in reasonable limits wit
 hout area penalties. We will showcase the signal-integrity aspects wrt GPI
 O pads and see how they were addressed.\n\nTopic: Back-End Design, Design,
  Engineering Tracks\n\nSession Chair: Badhri Uppiliappan (Analog Devices, 
 Inc. (ADI))
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