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DTSTAMP:20240626T180033Z
LOCATION:2008\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T110600
DTEND;TZID=America/Los_Angeles:20240626T112400
UID:dac_DAC 2024_sess186_BED113@linklings.com
SUMMARY:Si Backside Side-Channel Leakage and Simulation of Cryptographic I
 C Chips
DESCRIPTION:Back-End Design\n\nRikuu Hasegawa, Kazuki Monta, Takuya Wadats
 umi, Takuji Miki, and Makoto Nagata (Kobe University) and Lang Lin, Sreeja
  Chowdhury, Akhilesh Kumar, and Norman Chang (Ansys)\n\nFlip chip mounting
  has been widely used in recent years. Flip chip mounting has advantages s
 uch as shorter signal wires, smaller footprint, and multiple chip(lets).\n
  However, flip chip packaging makes Si substrate as an attack surface, and
  then Si substrate voltage becomes one of the side-channel information.\n 
 Therefore, we develop analysis flow of Si substrate voltage using Chip Pow
 er Model (CPM). CPM is made of power library of standard cells, logic tran
 sition of digital circuit, design data. In order to analyze an accurate Si
  substrate voltage, design data information that is required to create CPM
  includes Si substrate configuration, thickness, resistance, capacitance.C
 PM is created for each dataset with changing input vectors for side-channe
 l leakage evaluation.\n We confirm that side-channel attack is successful 
 using waveforms from CPM.\n Furthermore, we find the possibility of locali
 zed and chip thickness dependent noise propagation by analyzing of wavefor
 ms from CPM. As for locality, we also confirmed that the matching between 
 measurement and simulation.\n\nTopic: Back-End Design, Design, Engineering
  Tracks\n\nSession Chair: Badhri Uppiliappan (Analog Devices, Inc. (ADI))
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