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DTSTAMP:20240626T180033Z
LOCATION:2008\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T112400
DTEND;TZID=America/Los_Angeles:20240626T114200
UID:dac_DAC 2024_sess186_BED146@linklings.com
SUMMARY:System Aware IO Integrity Signoff
DESCRIPTION:Back-End Design\n\nAnubhav Johri and Bijaya Dash (Analog Devic
 es, Inc. (ADI))\n\nIO integrity analysis early in the design cycle helps d
 isintegrate the system level constraints from DIE level constraint. Integr
 ity challenges are more predominant with 324-529 BALL packages, in automot
 ive infotainment SOCs with close to 200-400 signals including GHz DDR, EMA
 C, eMMC, xSPI etc. Total power being supported ranging up to 10Watts. \n\n
 This paper discusses System aware IO integrity analysis which enables fast
 er engagement closure among design, test, and application/customer.\n\nTop
 ic: Back-End Design, Design, Engineering Tracks\n\nSession Chair: Badhri U
 ppiliappan (Analog Devices, Inc. (ADI))
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