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DTSTAMP:20240626T180034Z
LOCATION:2008\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T114200
DTEND;TZID=America/Los_Angeles:20240626T120000
UID:dac_DAC 2024_sess186_BED153@linklings.com
SUMMARY:Pre-Silicon Photon Emission Modeling and Optical Side-Channel Simu
 lation
DESCRIPTION:Back-End Design\n\nHenian Li (University of Florida); Lang Lin
 , Norman Chang, and Sreeja Chowdhury (Ansys); Kazuki Monta and Makoto Naga
 ta (Kobe University); and Mark Tehranipoor (University of Florida)\n\nOpti
 cal side-channel analysis poses a significant threat to the security of in
 tegrated circuits (ICs) by enabling the disclosure of secret data, such as
  encryption keys. In our work, we present a multiphysics simulation framew
 ork of optical side-channel analysis from the layout database of a fabrica
 ted testchip. By leveraging accurate device models and electro-photonic ph
 ysics, our framework models the photon emission behavior in ICs and enable
 s the statistical correlation of emitted photon patterns with secret keys.
  In our proposed solution, we begin by analyzing the device's layout under
  test and simulating the channel current of NMOS devices under various sti
 muli. By generating photon images based on pre-characterized models, we ov
 erlay individual photon images on the connected polysilicon ground metal. 
 Through lossless image processing, we extracted photon intensity patterns 
 from collected photon emission heatmaps and then performed correlation-bas
 ed photon emission analysis (CPEA) to disclose the security key byte by by
 te. Our framework enables IC designers to assess the risks associated with
  optical side-channel attacks and develop efficient countermeasures at the
  pre-silicon stage.\n\nTopic: Back-End Design, Design, Engineering Tracks\
 n\nSession Chair: Badhri Uppiliappan (Analog Devices, Inc. (ADI))
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