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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T133000
DTEND;TZID=America/Los_Angeles:20240626T134800
UID:dac_DAC 2024_sess189_ESS011@linklings.com
SUMMARY:No-Code Power and Clock System Design
DESCRIPTION:Embedded Systems and Software\n\nHoyeon Jeon, Ahchan Kim, and 
 Ingyu Kim (ITDA Semiconductor Co., Ltd.) and Jongbae Lee (BOS Semiconducto
 r Co., Ltd.)\n\nAI-driven computing demands more power, and power consumpt
 ion increases exponentially. However, fine-grained hardware-level power ma
 nagement can mitigate this issue. Compared to software-level management, i
 t can reduce power consumption by 20% to 60%.\n\nNevertheless, such manage
 ment adds complexity to hardware design, which can be challenging given fi
 xed design timelines. Within the conventional design process, multiple eng
 ineers participate at different stages of the design with only partial inf
 ormation, resulting in a complex and inefficient process.\n\nTo address th
 is, we introduce a no-code design platform for power and clock management 
 systems. This platform simplifies the design process, reduces setup and mo
 dification times, and has enabled our first customer to design their syste
 m quickly, meeting all specifications in line with automotive SOC standard
 s.\n\nOur no-code solution dramatically reduces design time and resource r
 equirements compared to traditional methods. The entire system configurati
 on process takes about one week, and design outputs are generated in just 
 few minutes.\n\nWith our no-code design platform, a single engineer can ef
 ficiently configure complex SOCs, significantly reducing idle power consum
 ption and design efforts for SOCs.\n\nTopic: AI, Embedded Systems, Enginee
 ring Tracks\n\nSession Chair: Frank Schirrmeister (Synopsys)
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