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DTSTAMP:20240626T180002Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240625T133000
DTEND;TZID=America/Los_Angeles:20240625T150000
UID:dac_DAC 2024_sess191@linklings.com
SUMMARY:Advanced Verification
DESCRIPTION:Front-End Design\n\nJoin us to learn about new strategies in t
 he catch-up game verification engineers play daily with the increasing des
 ign complexity and tighter schedules. In this session, presenters will sha
 re their wisdom across HLS, FuSa and hardware/software verification.\n\nA 
 Distributed Co-Simulation Environment and its Application in HW-FW Verific
 ation\n\nIn this talk, we present Cross Testbench (XTB), a distributed co-
 simulation environment that enables co-simulation across two simulation ap
 proaches, event-driven and cycle-based. Event-driven and cycle-based simul
 ation are two commonly utilized verification approaches in the industry. T
 he former tak...\n\n\nNitin Pundir, Pretty Jacob, Arun Joseph, Viresh Paru
 thi, Sandeep Korrapati, Ali El-Zein, Zoltan Hidvegi, and Bodo Hoppe (IBM)\
 n---------------------\nShift Left with Improved Power-Awareness in RTL St
 age Design for Early Design Verification\n\nRegister Transfer Logic (RTL) 
 of Digital on Top (DoT) SoC designs limited to logical integration.\nConve
 ntionally the early simulation framework involving digital RTL does not ha
 ve native power comprehension. The Power Intent (PI) is captured through C
 PF/UPF integration.\nThe Power and Ground (PG) IO ...\n\n\nPenchalkumar Ga
 jula and Lakshmanan Balasubramanian (Texas Instruments (India) Pvt. Ltd.);
  Gaurav Varshney (Texas Instruments); and Sooraj Sekhar, Siddharth Sarin, 
 Ruchi Shankar, Nikhita Gorja, and Nikhil Kumar (Texas Instruments (India) 
 Pvt. Ltd.)\n---------------------\nWho watches the watchman? FuSa Verifica
 tion of DCLS configuration through Formal and Static checks\n\nIncreasing 
 use of electronic components in safety-critical applications like healthca
 re, automobiles, etc. have made manufacturers aim for zero defects-per-bil
 lion deliveries. The onus is on the design and verification engineers to d
 eliver such high quality products without compromising on time-to-m...\n\n
 \nSayandeep Sanyal, Avinash Pandey, Srobona Mitra, Sathish Manickam, Aruna
 va Dutta, and Deepak Baranwal (Qualcomm)\n---------------------\nUse UVM  
 for AMS DFT through IEEE 1687 Procedural Description Language\n\nTime to m
 arket and bug free chip has put lot of pressure on the verification domain
  and resulted into multiple verification techniques that complement each o
 ther. UVM is reusable and robust verification environment. AMS verificatio
 n tests cases can be integrally fused in UVM and design module descri...\n
 \n\nHitu Sharma, Geert Seuren, and Rahul Lodwal (NXP Semiconductors)\n----
 -----------------\nEnhancing Quality and Reducing Verification Effort for 
 RTL Implementations against High-Level C/C++ Models using Formal Equivalen
 ce\n\nThe complexity of modern System on Chip (SoC) designs has led to adv
 anced verification techniques, facing the challenge of detecting undetecte
 d functional failures.\n\nIn the area of wireless and wireline communicati
 on products, designers initially model Digital Signal Processing (DSP) blo
 cks using hi...\n\n\nDavid Vincenzoni and Gianluca Rigano (STMicroelectron
 ics) and Gaetano Raia and Maurizio Martina (Politecnico di Torino)\n------
 ---------------\nSystematic Flow on AC Scan Timing/ATPG Constraint Generat
 ion\n\nDFT engineers take efforts on high quality SDC delivery in limited 
 schedule for timing analysis and ATPG. To meet the schedule, engineer ofte
 n got quality loss on false path consistency due to limited schedule or hu
 man error causing coverage loss or time wasted on timing violation review.
  APR timing...\n\n\nChen Yuan Kao and Yi Hsuan Chiu (Global Unichip Corpor
 ation)\n\nTopic: Design, Engineering Tracks, Front-End Design\n\nSession C
 hair: Dave Rich (Siemens)
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