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DTSTART:19700308T020000
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DTSTART:19701101T020000
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BEGIN:VEVENT
DTSTAMP:20240626T180034Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240625T144500
DTEND;TZID=America/Los_Angeles:20240625T150000
UID:dac_DAC 2024_sess191_FED017@linklings.com
SUMMARY:Systematic Flow on AC Scan Timing/ATPG Constraint Generation
DESCRIPTION:Front-End Design\n\nChen Yuan Kao and Yi Hsuan Chiu (Global Un
 ichip Corporation)\n\nDFT engineers take efforts on high quality SDC deliv
 ery in limited schedule for timing analysis and ATPG. To meet the schedule
 , engineer often got quality loss on false path consistency due to limited
  schedule or human error causing coverage loss or time wasted on timing vi
 olation review. APR timing closure progress will also be impacted. Moreove
 r, function constraint is often updated during timing closure progress. Fu
 nction constraint cannot be directly used in AC scan and referencing timin
 g report to prepare AC scan constraint often sacrifice test coverage. Prep
 aring AC scan constraint often takes time and rely on DFT engineer's exper
 ience to ensure the constraint quality.\nWe provided a systematic flow to 
 generate AC scan timing and ATPG constraint dealing with clock structure d
 ifference, unsupported description due to ATPG tool limitation, multiple t
 est mode for ATPG, and add-on/redundant timing exception due to Scan struc
 ture. The flow helps map AC scan clocks to function clocks and generate AC
  scan timing and ATPG constraints efficiently.\n\nTopic: Design, Engineeri
 ng Tracks, Front-End Design\n\nSession Chair: Dave Rich (Siemens)
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