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DTSTART:19700308T020000
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DTSTAMP:20240626T180034Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240625T133000
DTEND;TZID=America/Los_Angeles:20240625T134500
UID:dac_DAC 2024_sess191_FED073@linklings.com
SUMMARY:Use UVM  for AMS DFT through IEEE 1687 Procedural Description Lang
 uage
DESCRIPTION:Front-End Design\n\nHitu Sharma, Geert Seuren, and Rahul Lodwa
 l (NXP Semiconductors)\n\nTime to market and bug free chip has put lot of 
 pressure on the verification domain and resulted into multiple verificatio
 n techniques that complement each other. UVM is reusable and robust verifi
 cation environment. AMS verification tests cases can be integrally fused i
 n UVM and design module description at random abstraction level that allow
 s effective verification test setup. In this paper, we shall discuss how w
 e have extended the existing IEEE1687 flow to support analog signals. Than
  we talk about the approach with which verification engineer can effective
 ly reuse DFT test cases described in the IEEE 1687 Procedural Description 
 Language (PDL). PDL is suited to describe the digital setup of an AMS test
  and is written at IP level. It does guarantee a path to any production te
 st system therefore it is used to describe the AMS test cases as an input 
 for DFT Verification. The approach has the potential to improve the qualit
 y of DFT test cases and shall improve the overall code coverage of the AMS
  design.\n\nTopic: Design, Engineering Tracks, Front-End Design\n\nSession
  Chair: Dave Rich (Siemens)
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