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DTSTAMP:20240626T180034Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240625T134500
DTEND;TZID=America/Los_Angeles:20240625T140000
UID:dac_DAC 2024_sess191_FED080@linklings.com
SUMMARY:Shift Left with Improved Power-Awareness in RTL Stage Design for E
 arly Design Verification
DESCRIPTION:Front-End Design\n\nPenchalkumar Gajula and Lakshmanan Balasub
 ramanian (Texas Instruments (India) Pvt. Ltd.); Gaurav Varshney (Texas Ins
 truments); and Sooraj Sekhar, Siddharth Sarin, Ruchi Shankar, Nikhita Gorj
 a, and Nikhil Kumar (Texas Instruments (India) Pvt. Ltd.)\n\nRegister Tran
 sfer Logic (RTL) of Digital on Top (DoT) SoC designs limited to logical in
 tegration.\nConventionally the early simulation framework involving digita
 l RTL does not have native power comprehension. The Power Intent (PI) is c
 aptured through CPF/UPF integration.\nThe Power and Ground (PG) IO cells a
 re physical only cells (no logical connectivity), they are not inferred or
  instantiated in RTL.\nThis results in lack of \nBIASFET connectivity at R
 TL stage of design à BIASFET is the ESD trigger generated in a PGIO that d
 rives the primary protection devices in IO cells.\nLow Power (LP) checks t
 hrough PGIO paths.\nIt causes conventional DMS/AMS simulation setup to fai
 l if it involves IO functionality.\nIn most mixed-signal embedded processi
 ng SoCs, even the power-up fails à BIASFET connectivity impacts external r
 eset propagation.\nThe proposed solution is Compatible with standard/semi-
 custom implementation flows.\nComplete coherence across design, implementa
 tion and verification flows.\nEnables concurrent execution of LP verificat
 ion and Physical Design (PD) cycles.\nEnables early generation of Power Aw
 are (PA) netlist, hence early verification of power intent with PG I/Os aw
 are RTL.\nEliminates manual work-arounds in traditional LP mixed-signal/an
 alog verification.\nVerifying the chip level ESD integration across digita
 l domains at early stage of the design using PA-RTL and avoid risk due to 
 late finding of ESD triggering risk in the designs.\nDebugging of ESD prot
 ection circuit integration issues at early stage.\nAs a result, overall de
 sign cycle time and RTL freeze quality improved.\nConventionally issues wi
 th ESD architecture including BIAS connectivity and can only be identified
  at post synthesis Gate Level (GL) stage à At least 3 months later than RT
 L stage.\n\nTopic: Design, Engineering Tracks, Front-End Design\n\nSession
  Chair: Dave Rich (Siemens)
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