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DTSTART:19700308T020000
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DTSTAMP:20240626T180034Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240625T143000
DTEND;TZID=America/Los_Angeles:20240625T144500
UID:dac_DAC 2024_sess191_FED082@linklings.com
SUMMARY:Who watches the watchman? FuSa Verification of DCLS configuration 
 through Formal and Static checks
DESCRIPTION:Front-End Design\n\nSayandeep Sanyal, Avinash Pandey, Srobona 
 Mitra, Sathish Manickam, Arunava Dutta, and Deepak Baranwal (Qualcomm)\n\n
 Increasing use of electronic components in safety-critical applications li
 ke healthcare, automobiles, etc. have made manufacturers aim for zero defe
 cts-per-billion deliveries. The onus is on the design and verification eng
 ineers to deliver such high quality products without compromising on time-
 to-market metrices. Dual Core Lock Step (DCLS) is a configuration that is 
 used widely in Functional Safety (FuSa) applications to alert the user whe
 never a system deviates from its specified behaviour. Given many possible 
 implementations of the DCLS configuration, verification of a DCLS implemen
 ation becomes a challenging tasks. In this work, we present a generic DCLS
  verification package which uses formal and static checks to verify all as
 pects of a DCLS implementation. We demonstrate some of the bugs and detail
  out our prosposed checks which have been successfully applied on mulitple
  in-house designs.\n\nTopic: Design, Engineering Tracks, Front-End Design\
 n\nSession Chair: Dave Rich (Siemens)
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