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BEGIN:VEVENT
DTSTAMP:20240626T180002Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T103000
DTEND;TZID=America/Los_Angeles:20240626T120000
UID:dac_DAC 2024_sess192@linklings.com
SUMMARY:Industry Trends in the Front End
DESCRIPTION:Front-End Design\n\nEmergence of AI has fueled an arms race to
  design new kinds of hardware to run them optimally and that in turn is ac
 celerating innovation in design and verification methodologies. Come and l
 earn the latest industry trends in front-end design, from Co-pilots in des
 ign and verification to improving PPA using AI.\n\nDesign Constraint Strat
 egy For Dealing With Cascaded Clock MUX Structures\n\nThe presence of mult
 iple and cascaded clock MUX structures can be seen in complex RTL/digital 
 desings. The existing CDC static verification tools, Synthesis tools and S
 tatic Timing Analysis (STA) tools have a hard time analyzing the operation
  modes of clock multiplexers (clock MUX in short), especia...\n\n\nAnish K
 eshava, Aakarshak Nandwani, Nitesh S, Satyanarayana Patnala, and Sridharr 
 S (Synopsys)\n---------------------\nAugmenting IP/SOC Verification Exhaus
 tiveness with BER Transformer infused Deep Learning Model\n\nIn the realm 
 of ever evolving Semiconductor technology landscape with complex SoC's and
  Systems , integration of Chat GPT like AI Transformers in IP/SoC Design V
 erification could potentially revolutionize a transformative wave of autom
 ating verification there by contributing to increased robustness ...\n\n\n
 Anil Deshpande, Somasunder Sreenath, Mukesh Barnwal, Rohan R, and Swapnil 
 Singh (Samsung Semiconductor)\n---------------------\nAI-Powered High-Sigm
 a Automated Full Library Verification Methodology for Standard Cells\n\nTh
 is paper addresses the critical challenge in chip design scalability, wher
 e standard cells are replicated in the millions, resulting in designs with
  tens of billions of transistors. Traditional methods of constraining Proc
 ess, Voltage, and Temperature (PVT) corners based on past experiences and 
 co...\n\n\nChengcheng Liu (NVIDIA) and Mohamed Atoua (Siemens)\n----------
 -----------\nImproving Power Efficiency using Workload-aware PPA Analysis 
 for AI Engine\n\nWith the increasing demand of AI and ML applications, the
  need for specialized hardware designs becomes imperative to achieve high 
 performance and energy efficiency in computing. Our AI Engines (AIE) are d
 eveloped to proficiently accelerate such workloads, particularly for compl
 ex ML models with com...\n\n\nSeokjoong Kim, Alex Hao, Reza Sajadiany, Pan
 telis Sarais, and Tim Tuan (Advanced Micro Devices (AMD))\n---------------
 ------\nShift Left Detection and Root Cause Analysis of Synthesis Optimize
 d Registers at RTL Level\n\nThe presentation focuses on bridging the gap b
 etween RTL designers and Implementation engineers. Removal of registers du
 ring the synthesis stage without providing any root cause analysis poses s
 ignificant challenges for Implementation engineers late in the cycle. At t
 he same time, currently there is...\n\n\nSathappan Palaniappan (Broadcom) 
 and Kartik Agarwal, Himanshu Kathuria, Jaskaran Ajimal, Amit Jalota, and H
 arsha Somashekar (Synopsys)\n\nTopic: AI, Design, Engineering Tracks, Fron
 t-End Design\n\nSession Chair: Vikas Sachdeva (Real Intent)
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