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DTSTAMP:20240626T180034Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T103000
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UID:dac_DAC 2024_sess192_FED028@linklings.com
SUMMARY:AI-Powered High-Sigma Automated Full Library Verification Methodol
 ogy for Standard Cells
DESCRIPTION:Front-End Design\n\nChengcheng Liu (NVIDIA) and Mohamed Atoua 
 (Siemens)\n\nThis paper addresses the critical challenge in chip design sc
 alability, where standard cells are replicated in the millions, resulting 
 in designs with tens of billions of transistors. Traditional methods of co
 nstraining Process, Voltage, and Temperature (PVT) corners based on past e
 xperiences and conducting Monte Carlo simulations on worst-case scenarios 
 prove unreliable. Incorrectly predicting worst-case PVT can lead to schedu
 le delays and design robustness issues. The brute-force Monte Carlo method
 s for high sigma verification are both costly and impractical. \n\nTo over
 come these challenges, we present an AI-powered automated methodology for 
 detecting and verifying worst-case yield. Our single-pass PVT + variation 
 high-sigma solution, exemplified by the Solido PVTMC Verifier, achieves th
 e fastest runtime, while the brute-force accurate high-sigma solution, dem
 onstrated by Solido High-Sigma Verifier, ensures the highest accuracy. \n\
 nThe results on latch-based D flip-flop circuits showcase the effectivenes
 s of our approach. Solido High-Sigma Verifier verified bimodality failure 
 occurrences with 4,000 simulations, delivering a staggering 2,500,000X fas
 ter runtime than brute-force methods. Furthermore, the yield for this cell
  at the target PVT was verified to 6.322 sigma, accompanied by a remarkabl
 e 30X runtime speedup compared to the previous methodology. This signifies
  not only improved performance but also better accuracy and coverage rates
 .\n\nTopic: AI, Design, Engineering Tracks, Front-End Design\n\nSession Ch
 air: Vikas Sachdeva (Real Intent)
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