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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20240626T180034Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T114200
DTEND;TZID=America/Los_Angeles:20240626T120000
UID:dac_DAC 2024_sess192_FED070@linklings.com
SUMMARY:Design Constraint Strategy For Dealing With Cascaded Clock MUX Str
 uctures
DESCRIPTION:Front-End Design\n\nAnish Keshava, Aakarshak Nandwani, Nitesh 
 S, Satyanarayana Patnala, and Sridharr S (Synopsys)\n\nThe presence of mul
 tiple and cascaded clock MUX structures can be seen in complex RTL/digital
  desings. The existing CDC static verification tools, Synthesis tools and 
 Static Timing Analysis (STA) tools have a hard time analyzing the operatio
 n modes of clock multiplexers (clock MUX in short), especially if they are
  glitch free switching circuits that may not resemble a simple multiplexer
  to the tools. For uch clock MUX structures, relevant design constraints (
 or SDCs) need to be added to guide the static tools. In this proposal we h
 ave a series of well-defined generated clock and logically exclusive const
 raints that will help cover all the combinations of clock propagations thr
 ough any complex clock MUX structure in the design. This will enable smoot
 h CDC, synthesis and timing verification of the design considering all the
  clocks input to the clock MUX, in an accurate manner. This technique yiel
 ds accurate results from an STA and a synthesis perspective. This techniqu
 e helps to reduce the number of case analysis modes needed (which is essen
 tially to propagate only one fixed clock through a clock MUX in that mode)
 , meaning that it can do the heavy lifting of all the analysis modes at on
 e go, thereby reducing the turnaround time considerably. The coverage of a
 ll combinations of clocks is now possible in one single CDC static verific
 ation run, which also eliminates the noise in CDC reports where there were
  overlapping violations across analysis modes previously. With such promis
 ing results, there is also scope for automation of this technique provided
  the relevant data is available as input.\n\nTopic: AI, Design, Engineerin
 g Tracks, Front-End Design\n\nSession Chair: Vikas Sachdeva (Real Intent)
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