BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180034Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T110600
DTEND;TZID=America/Los_Angeles:20240626T112400
UID:dac_DAC 2024_sess192_FED089@linklings.com
SUMMARY:Augmenting IP/SOC Verification Exhaustiveness with BER Transformer
  infused Deep Learning Model
DESCRIPTION:Front-End Design\n\nAnil Deshpande, Somasunder Sreenath, Mukes
 h Barnwal, Rohan R, and Swapnil Singh (Samsung Semiconductor)\n\nIn the re
 alm of ever evolving Semiconductor technology landscape with complex SoC's
  and Systems , integration of Chat GPT like AI Transformers in IP/SoC Desi
 gn Verification could potentially revolutionize a transformative wave of a
 utomating verification there by contributing to increased robustness of de
 signs. \n\nIP and SOCs underpin many modern electronic systems like HPC/AI
  and Automotive SoC's. While functional correctness is crucial, it no long
 er suffices for real-world applications and usage. In this paper we have e
 xplored to utilize the power of light-weight generative AI BER Transformer
  Model in verification as it redefines the possibilities of how we interac
 t with textual data, including hardware design specifications and taking v
 erification to completeness by suggesting extra scenarios for Performance 
 and Security aspects . It bridges the gap between 'what' a system does, 'h
 ow well' it performs, and 'how securely' it operates and addresses the gre
 y areas in system level verification which cannot be captured at IP or sub
 -system level.\n\n We can scale this model to SOC level and try to address
  verification challenges for miscellaneous SOC IP's like GPIO,DFT mux, Low
 er Power Elements and Safety Elements. \n\nThis paper highlights the power
  of using Generative AI in verification, Augmenting AI with verification c
 an help us catch bugs/issues early in the verification life cycle.\n\nTopi
 c: AI, Design, Engineering Tracks, Front-End Design\n\nSession Chair: Vika
 s Sachdeva (Real Intent)
END:VEVENT
END:VCALENDAR