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DTSTART:19700308T020000
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DTSTAMP:20240626T180033Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T104800
DTEND;TZID=America/Los_Angeles:20240626T110600
UID:dac_DAC 2024_sess192_FED105@linklings.com
SUMMARY:Improving Power Efficiency using Workload-aware PPA Analysis for A
 I Engine
DESCRIPTION:Front-End Design\n\nSeokjoong Kim, Alex Hao, Reza Sajadiany, P
 antelis Sarais, and Tim Tuan (Advanced Micro Devices (AMD))\n\nWith the in
 creasing demand of AI and ML applications, the need for specialized hardwa
 re designs becomes imperative to achieve high performance and energy effic
 iency in computing. Our AI Engines (AIE) are developed to proficiently acc
 elerate such workloads, particularly for complex ML models with competitiv
 e energy efficiency. For the energy efficient computing in AIE, we develop
 ed a workload-aware power analysis methodology to push the limits of PPA t
 argets, and started Shift Left at the early stage of RTL design for AIE in
  Ryzen, Epyc and Versal product families. The framework includes power vec
 tor generation, automatic workload selection, power report analysis, creat
 ion of power model at RTL level. In addition to the early power estimation
 s for design changes at RTL level, it generates AIE core pipeline instruct
 ion statistics used in AIE advanced power modeling training procedure and 
 other valuable information such as data dependencies that can increase acc
 uracy of power model. We observed that dynamic power and CG related metric
  WCPP were significantly improved by average 27% and 56% respectively, thr
 oughout the AIE IP design developments.\n\nTopic: AI, Design, Engineering 
 Tracks, Front-End Design\n\nSession Chair: Vikas Sachdeva (Real Intent)
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