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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:2008\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240625T133000
DTEND;TZID=America/Los_Angeles:20240625T150000
UID:dac_DAC 2024_sess201_IP087@linklings.com
SUMMARY:Technology and IP Scaling Beyond 5nm
DESCRIPTION:IP\n\nArif Khan and Gopi Ranganathan (Cadence Design Systems, 
 Inc.); Nazar Zaidi (Advanced Micro Devices (AMD)); Kaizad Mistry (Intel Co
 rporation); and Lluis Paris (TSMC)\n\nThis session addresses the frontiers
  of technology scaling, examining the interplay between cost, performance,
  and power as designers navigate current limitations and future trends. Di
 scussions will range from the evolution of process technology, such as Fin
 FET to GAA, to the strategic use of DTCO and disaggregated designs in over
 coming die size and cost-per-transistor challenges. Emphasizing the critic
 al role of packaging in adopting chiplets, advances in interconnect and 3D
 -IC technologies will be explored. The collective insights aim to chart a 
 course through the complexities of scaling in the more-than-Moore era, foc
 using on economic and technological viability.\n\nTopic: Engineering Track
 s, IP
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