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DTSTAMP:20240626T180034Z
LOCATION:2012\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240626T140600
DTEND;TZID=America/Los_Angeles:20240626T142400
UID:dac_DAC 2024_sess204_IP060@linklings.com
SUMMARY:Droop! There it is!
DESCRIPTION:IP\n\nMichael Durr (Movellus)\n\nSoCs designed for compute-int
 ensive workloads, such as AI training and inferencing, continue to grow an
 d power budgets are increasing geometrically. Power consumption is compris
 ed of dynamic and static power elements. The latter is generally fixed and
  determined by process technology and design techniques, while the former 
 depends on workloads and frequency. This variability of workloads can driv
 e rapid changes in current draw, which causes voltage droop, a rapid drop 
 in power rails that can lead to timing glitches and system failures. For e
 xample, sudden changes in models or weights can drive these sudden shifts 
 in workloads causing voltage droops.\n\nSilicon design teams have attempte
 d to address droop in various ways, but all methods have significant downs
 ides. The typical options employed are increasing voltage margins, reducin
 g operating frequencies, scheduling workloads through software, or using a
 ctive droop mitigation methods that may be fully custom or tailored to the
 ir needs. Each of these solutions has advantages and drawbacks regarding p
 ower, performance, and implementation effort.\n\nThis discussion will expl
 ore the root causes of droop, its impact on power, and the increasing chal
 lenges in advanced nodes.  It will also delve into modern droop mitigation
  techniques, highlighting the advantages of a tightly-coupled, synthesizab
 le solution.\n\nTopic: Engineering Tracks, IP\n\nSession Chair: Vidyasagar
  Ganesan (Advanced Micro Devices (AMD))
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