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DTSTAMP:20240626T180033Z
LOCATION:2012\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240625T140000
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UID:dac_DAC 2024_sess206_IP078@linklings.com
SUMMARY:Automated Design Scenario Extraction From A Large Design For Faste
 r Debug Of Static Verification Tools
DESCRIPTION:IP\n\nGaurav Pratap, Vishal Keswani, Sachin Bansal, Amit Goldi
 e, and Sanjay Gulati (Synopsys)\n\nIn recent times, Increased size of SOC 
 has made static verification time and memory consuming. In a SOC which con
 tains billions of design elements, few cases of missing/false violations o
 r large run time issues get reported by customer on any static tool. When 
 such issues get reported at the time of final sign off stage of the chip, 
 they become a gating issue for any static tool. In such case static tool v
 endors are expected to provide the fix in the tool on urgent priority.\nTo
  fix any issue in the tool R&D engineer need to first identify root cause 
 of the issue. Below methods are the traditional ways of root cause identif
 ication in a big design:\n        1.        Using debug prints \n        2
 .        Apply debugger on code execution\n        3.        Code profilin
 g tools \n        4.        Reducing the size of design by making unrelate
 d portion of design as Blackbox model         \n\nFinding the root cause o
 f the issue using above mentioned ways and provide quick fix in tool takes
  time as:-\n        R&D, AE may not have direct access to design.\n       
  Shipping design to a secure network is difficult or takes time\n        H
 igh number of debug prints make it difficult to find root cause\n        A
 ttaching debuggers on large design is cumbersome and slow\n        From th
 e debug fields in violations and other reports, R&D or field only has limi
 ted knowledge about the design scenarios. It is difficult to create a unit
  reproducer\nIt has often been observed that having a small reproducer in 
 hand reduces the turnaround time significantly for delivery of the fix. To
  overcome this challenge we have developed an utility in our tool which pr
 ovides us a capability to create a small reproducer out of the big design.
 \n\nTopic: Engineering Tracks, IP\n\nSession Chair: Himanshu Sanghavi (Met
 a)
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