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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:2012\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240625T141500
DTEND;TZID=America/Los_Angeles:20240625T143000
UID:dac_DAC 2024_sess206_IP079@linklings.com
SUMMARY:Watt's Up with DDR5: Formal Verification Framework for Robust DRAM
  Power Management
DESCRIPTION:IP\n\nPradip Prajapati, Anshul Jain, Mounica Kothi, Erin Rasmu
 ssen, and Rocco Salvia (Intel Corporation)\n\nThe latest generation of DDR
 5 synchronous dynamic random-access memory (DRAM) brings significant advan
 cements over its predecessor, DDR4. These improvements are particularly be
 neficial in data-intensive applications such as cloud computing, big data 
 analytics, and high-performance computing. DDR5 enhances performance and p
 ower efficiency, but it also introduces new technical challenges in design
  implementation and verification, especially from the Memory Controller (M
 C) perspective.\nThe design and verification of power management flows for
  DDR5 DRAM require addressing several major technical challenges. To ensur
 e exhaustive validation of power management flows, a Formal Property Verif
 ication (FPV) based methodology is employed. This approach has yielded enc
 ouraging results, highlighting the successful optimization of DDR5 DRAM Po
 wer Management.\nThe verification of DDR5 Power Management using formal te
 chnology has led to a detailed formal verification framework that validate
 s power management flows. The results have been promising in terms of bugs
  found and coverage achieved. This has led to improved accuracy and effici
 ency of the DDR5 DRAM Memory Controller.\nThe successful verification and 
 validation of DDR5 DRAM's power management flows demonstrate the effective
 ness of the FPV-based methodology. This advancement is crucial for the con
 tinued evolution of memory technologies in high-demand computing environme
 nts.\n\nTopic: Engineering Tracks, IP\n\nSession Chair: Himanshu Sanghavi 
 (Meta)
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