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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:2012\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20240625T144500
DTEND;TZID=America/Los_Angeles:20240625T150000
UID:dac_DAC 2024_sess206_IP081@linklings.com
SUMMARY:Enabling Protocol Validation of High Speed Serial Links using SerD
 es to transfer data between PHY Chip and Link layer on FPGA
DESCRIPTION:IP\n\nPriyanka Goel, Aashish Bhide, Vivek Uppal, Ameer Youssef
 , and Nitin Sharma (Synopsys)\n\nEver increasing demand for higher data tr
 ansfer speed leads to evolution of new Serial link protocols and advanceme
 nt in existing one. Implementation and support of these Serial link protoc
 ols require evolution of PHY and Controller. PHY IPs require to be tested 
 upfront on Silicon Chip (PHY IPs are Analog- Mixed Signal IPs) for every t
 echnology node/Foundry. Data from this PHY Chip needs to be transferred to
  FPGA for validation with Controller. Increase in bit rate poses a signifi
 cant challenge due to need for large number of GPIOs in the PHY chip. This
  increased number of GPIOs increase the size in PAD limited PHY Chip which
  increases the cost. To address this problem, proposed solution is to use 
 lanes of lower speed SerDes to transfer data between PHY Chip and FPGA ins
 tead of multiple parallel GPIOs\n\nTopic: Engineering Tracks, IP\n\nSessio
 n Chair: Himanshu Sanghavi (Meta)
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