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TZOFFSETFROM:-0700
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UID:dac_DAC 2024_sess209_WKSHP103@linklings.com
SUMMARY:GREAT: Gen-AI Research in Electronic Design, Automation, and Test
DESCRIPTION:Workshop\n\nRamesh Karri and Siddharth Garg (New York Universi
 ty) and Jeyavijayan Rajendran (Texas A&M University)\n\nLarge language mod
 els (LLMs) have been a significant breakthrough in artificial intelligence
 , demonstrating remarkable success in solving various real-world problems.
  These models, trained on vast amounts of text data, have shown an uncanny
  ability to generate human-like text, understand context, answer questions
 , and write code. They have been successfully deployed in numerous applica
 tions, including customer service, content creation, and language translat
 ion, to name a few. The versatility and robustness of LLMs have made them 
 an invaluable tool in the AI toolkit, opening up avenues for exploration a
 nd innovation. Microsoft, Google, Meta, and Amazon have invested in genera
 tive AI technologies like LLMs.\n\nOne such avenue that has garnered atten
 tion is using LLMs in chip design. Digital chip design, a complex and intr
 icate process, involves the creation of integrated circuits used in variou
 s electronic devices. LLMs are expected to aid designers during design and
  concept development, verification, validation, and security checks. For i
 nstance, Synopsys has recently developed an LLM-based framework to aid chi
 p design and development.\n\nWith these revolutionary developments and int
 erest from leading electronic design automation companies (Cadence, Synops
 ys, Siemens) and chip design companies (Intel, Nvidia, Qualcomm, IBM, etc.
 ), there is an increasing need for a greater understanding of LLMs' roles 
 in EDA. We are organizing this first "Workshop on Gen-AI for Chip Design",
  consisting of:\n\n(i) Introductory session on LLMs for chip design (1:00-
 1:30)\n\n(ii) Three-hour "Design a Chip in a Day" competition (e.g., RTL g
 eneration and testing) open to the EDA, AI, and Design community (students
 , academics, practitioners, hobbyists) (1:30-4:30)\n\n(iv) Closing session
  on the next steps (4:30-5:00)\nTogether, these sessions will highlight th
 e advances of LLMs for chip design, research adventures in academia, and p
 rovide hands-on experience for LLM-based chip design.\n\nCompetition Regis
 tration Link: https://forms.gle/UDnp2xs9gVzxCm3t9\n\nCompetition Flyer: ht
 tps://shorturl.at/8Jhzv\n\nTopic: AI
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