BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Los_Angeles X-LIC-LOCATION:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240626T180002Z LOCATION:Level 2 Exhibit Hall DTSTART;TZID=America/Los_Angeles:20240624T170000 DTEND;TZID=America/Los_Angeles:20240624T180000 UID:dac_DAC 2024_sess232@linklings.com SUMMARY:Monday Engineering Track Poster Reception DESCRIPTION:Engineering Track Poster\n\nAccelerate RF Board BOM Simulation with ADS Design Automation\n\nThe Keysight ADS RF board design automation tool has significantly improved the efficiency of Bill of Material simula tion and brings down the work needed for an engineer to validate a typical RF board down from 14 days to 1.5 day. The approach and tooling are used by a major smart phone developer. ...\n\n\nZhen ZHANG, Tom Demuer, Juneyi PENG, and Shengkang ZHANG (Keysight Technologies)\n---------------------\ nSolving Memory Subsystem Verification Challenges for Multi-Instance Desig ns\n\nThis paper talks about the importance of the higher memory sub syste m level verification needs for protocol compliance of recent generation of memory sub systems using DDR like DDR5, Lpddr5 and how Cadence verificati on IP memory model team has come up/implemented a generic solution to desc ribe such ...\n\n\nShyam Sharma and Manish Chand (Cadence Design Systems, Inc.)\n---------------------\nCharting Uncharted Waters: Functional Simula tion Reshaping CDC/RDC Constraints Signoff\n\nClock Domain Crossing (CDC)a nd Reset Domain crossing(RDC) checks signoff poses several challenges in d igital design, and addressing these challenges is crucial for ensuring the reliability and correctness of complex SoC's. While static analysis tools provide critical role in CDC/ RDC analysis, funct...\n\n\nsuhas S, Deepma la Sachan, Ponsankar Arumugam, and Ritesh Jain (Intel Corporation)\n------ ---------------\nHolistic Approach on 3DIC Planning\n\n3DIC design plannin g has been one of the interesting and challenging areas of research and de velopment in recent times due to its higher demand and technological impro vement that can cater to latest requirements in IC design.\nThis piece of work has been carried out to explore the different ventures ...\n\n\nVenka ta Chinni, SRUTI L SHRIDHAR, Tadasa Mahapatra, and Sandeep Jadhav (Samsung )\n---------------------\nBus Delay Skew Minimization for High Bandwidth M emory Designs\n\nHigh bandwidth memory (HBM) consists of several memory ch ips and a dedicated buffer die that serializes and de-serializes data for processing and transferring. One major parameter deciding the performance of a buffer die is the number of parallel signal buslines spanning half th e die between signal ...\n\n\nKwangok Jeong, Seoklip Ki, and Sua Kim (Sams ung) and Alpesh Kothari, Jaejun Lee, JeongGuk Choi, Raghu Gude, and Sung-S oon Choi (Siemens)\n---------------------\nAccelerating Automated Custom L ayout Creation Through Smart Design Intent Migration\n\nWith the semicondu ctor industry's push to newer process nodes and shorter time to market, an alog and custom IC layout creation is turning out to be the bottleneck as it has historically been a highly manual process. Since Analog IPs often s tay the same across nodes, the ability to automatically recr...\n\n\nGiris h Vaidyanathan and Sravasti Nair (Cadence Design Systems, Inc.)\n--------- ------------\nFaster Timing Closure of Multiple Power Domains Based Design s with SMVA\n\nMulti-voltage SoC's with uncorrelated supplies are becoming predominantly common with a lot of devices coming up in the market with l ow power requirements. Here, Non-timing critical blocks are designed at lo wer voltage (power saving) and High-performance blocks are designed at hig her voltage (desire...\n\n\nRajnish GARG and Rohit Goel (STMicroelectronic s)\n---------------------\nThe Designer's Superpower! Early Circuit Verifi cation with Calibre nmLVS Recon\n\nIncreasing complexity in integrated cir cuits (ICs) node over node results significant growth in circuit verificat ion time and effort. Today's tapeout sensitivities make it critical to beg in checking and fixing connectivity issues in earlier design stages, since connectivity violations will affect do...\n\n\nKesmat Shahin (Siemens); R ahul Sai T Govindaswamy (Google); Smitha Shivaji Kamathi and Anish Padhi ( Siemens); Rakesh Reddy, Karishma Qureshi, and Rajashekar Sura (Google); an d Gurpreet Singh Lamba (Siemens)\n---------------------\nReducing Interlay er misalignment caused by BLE (Bulk Layout Effect) : Solutions for improvi ng in-chip uniformity of alignment between two layers\n\nAs DRAM devices c ontinue to shrink, defects that are out of tolerance have become more prev alent. One such defect is interlayer misalignment, which occurs when two l ayers are not aligned correctly. Interlayer misalignment caused by the shi fted patterns due to heat and stress is called as BLE (Bulk L...\n\n\nHyej in Kim, Ohhun Kwon, Jichang Sim, Daehee Lee, Hyunmi Ji, and Jooseong Lee ( Samsung)\n---------------------\nAdvancing Low Power Design in the Era of Rising Energy Footprints: Insights from IEEE 2416 Standard and Future Exte nsions\n\nIn the current dynamically changing landscape of computing, grow th of artificial intelligence (AI) applications have caused an exponential increase in energy consumption, re-emphasizing the need for managing powe r footprint in chip design. To manage this escalating energy footprint and enabling true...\n\n\nNagu Dhanwada (IBM); Jerry Frenkil (Si2, Inc.); W. Rhett Davis (North Carolina State University); Daniel Cross (Cadence Desig n Systems, Inc.); Akil Sutton (IBM); and Ali Sadigh and Leigh-Anne Cleveng er (Si2, Inc.)\n---------------------\nOvercoming the Growing Challenge of IR Drop by Effective Power Grid Enhancement during Chip Finishing\n\nInte grated circuit (IC) Power management is a growing challenge for both desig ners and manufacturers at advanced process nodes. We introduce an analysis -based solution during chipfinishing flow. This innovative solution provid es automated DRC-clean layout modifications that reduce IR drop without ne ...\n\n\nRahul Sai T Govindaswamy (Google); Smitha Shivaji Kamathi and Ben Allen (Siemens); Ravikanth Kosuru and Prateek Pendyala (Google); and Zvar t Askanazyan, Christian Miles, Heba Sharaf, Esraa Swilliam, Jeff Wilson, a nd Gurpreet Lamba (Siemens)\n---------------------\nAn Effective Method of Evaluating Chip Power Noise in System-level with iCPM\n\nWith the continu ous advancement of advanced chip packaging technology, the excellent perfo rmance of package core power plays a pivotal role in the operation of the entire chip. Especially for high-performance 2.5D and 3D large-scale ICs, the efficient simulation of core power poses significant chall...\n\n\nChe nxi Yang (Sanechips Technology Co.,Ltd); Yongsheng Guo (Ansys); Ping Ding (Sanechips Technology Co.,Ltd); Li Zou (Ansys); and Feng Wu, Jiangtao Zhan g, jianguo zhang, and Keqing Ouyang (Sanechips Technology Co.,Ltd)\n------ ---------------\nEfficient HBM Channel Design in 2.5D Silicon Interposer w ith Signal Integrity Optimization\n\nHigh Bandwidth Memory (HBM) in 2.5D i nterposers is to address the need for increased memory bandwidth in AI and HPC applications. HBM channel design is crucial for achieving the high-sp eed data transfers. However, routing such a channel is challenging due to the tight interconnections and the need t...\n\n\nFeng Ling and Yan Ma (Xp eedic)\n---------------------\nForward Progress Testing: Saftey vs Livenes s Assertion\n\nFormal verification plays a crucial role in today's Design Verification flows. There's no doubt that Formal verification does tasks t hat are extremely difficult in Simulation-based verification. One such tas k is checking forward progress in a System, ensuring that a system eventua lly reaches a desir...\n\n\nAnkit Kumar Garg (NVIDIA)\n------------------- --\nA Novel approach to implement FuSA Feature in Complex Automotive SoCs Using USF\n\nOne of the critical requirements for any embedded application is FuSA (Functional Safety) because it is essential that all the embedded devices function correctly and safely under any faulty or failure scenari os. When it comes to automotives, as per ISO 26262 standard, any failure, be it systematic ...\n\n\nDEEPTI KHURANA and Manikanta Akula (NXP Semicond uctors)\n---------------------\n3DIC prototype design and transient early thermal analysis\n\n3DIC design can reduce the length of interconnections and secure gains in power and performance by using multiple dies stacked v ertically.\nHowever, the design complexity increases, and more resources a re required to modify the design compared to a single die design.\nIn the early stages of design, we...\n\n\nYongjin Hong, Kiwook Jung, Ki-Ok Kim, B yunghyun Lee, and Sangyun Kim (Samsung)\n---------------------\nSystematic Verification Framework for Memory Subsystem Ensuring Reliability and Robu stness\n\nThe vertical segments across IoT, data centers, AI, networking, autonomous vehicles, cryptocurrency infrastructure are creating data requi rements explosion. New standards, emerging at lightning speeds, are battli ng the never-ending thirst for low power, high speed and throughput. With the increase i...\n\n\nVatsal Patel, Pooja Patel, Dharini SubashChandran, Ritesh Desai, and Pratibha Sukhija (Cadence Design Systems, Inc.)\n------- --------------\nA "Shift-Left" Analysis Flow For Layout Parasitics Of High Speed Analog Mixed Signal Design\n\nFor today's high speed AMS design, as the processes shrinking and design complexity increasing, the layout para sitics have become more and more important and even more dominant than dev ices, which impact a lot on design's performance.On the other hand, as the parasitics magnitude increase, it's more...\n\n\nwei wei, Yaping Huang, a nd Jie Hu (Sanechips Technology Co.,Ltd); Xiaomei You (Ansys); and Wei Wei (Sanechips Technology Co.,Ltd)\n---------------------\nAutomated Floorpla n Scaling Solutions and Framework\n\nConventional hierarchical design plan ning flows are neither runtime efficient nor resource efficient for a) qui ck floorplan porting during process node evaluation and library bring up w ith minimal dependency or b) what-if exploration to hasten block convergen ce with improved local FP optimization an...\n\n\nSivaramakrishnan Harihar a Subramanian, Venkatesh RS, and Khris Valencia Chacon (Intel Corporation) \n---------------------\nUnified Waveform Analysis Platform for Tr.-Level Design Verification\n\nThis paper presents a software tool designed to str eamline the transistor-level design verification process. The tool excels in managing and integrating multiple waveform formats, such as Synopsys FS DB and Cadence TRN/VWDB, into a unified platform. This integration enhance s the verification process'...\n\n\nChoi Wonwoo, Kwangsun Kim, Sungho Park , Hyungjung Seo, Younsik Park, and Jungyun Choi (Samsung)\n--------------- ------\nSystematic Flow on AC Scan Timing/ATPG Constraint Generation\n\nDF T engineers take efforts on high quality SDC delivery in limited schedule for timing analysis and ATPG. To meet the schedule, engineer often got qua lity loss on false path consistency due to limited schedule or human error causing coverage loss or time wasted on timing violation review. APR timi ng...\n\n\nChen Yuan Kao and Yi Hsuan Chiu (Global Unichip Corporation)\n- --------------------\nLeveraging several automated techniques and methodol ogies for faster coverage closure and design sign-off\n\nBottlenecks in De sign verification sign-off process during project execution: \n 1. Cove rage closure \n 2. Regression management \nProblems faced during Cover age closure :\n 1. Multiple iterations of regressions\n 2. Coverin g all the bins (Lakhs of bins in current RTL designs)\n 3. Anal...\n\n \nGulshan Sharma and Sougata Bhattacharjee (Samsung)\n-------------------- -\nModeling Optimal Number of Tap-points for Flexible H-tree During Clock Tree Synthesis\n\nClock tree synthesis is the process of connecting the cl ocks to all clock pins of sequential circuits by using inverters or buffer s in order to balance the skew and minimize the insertion delay. There are multiple techniques available for clock distribution. Some of these metho ds include the single ...\n\n\nAnup kumar and Akshay Mankotia (Cadence Des ign Systems, Inc.)\n---------------------\nAn Integrated Behavioral Modeli ng Method for Mixed Signal IPs\n\nThe shrinking technologies have paved th e path for complex devices having various functionalities integrating vari ous IPs in a single SoC and hence, complex clocking structure and efficien t power management in AMS IP are gaining popularity. The same design comp lexity is reflected in HDL behavior mo...\n\n\nBhupendra Singh, Rahul Kuma r, Pallav Kumar, Jean-Aranud Francois, Mitu Mittal, and Anil Dwivedi (STMi croelectronics)\n---------------------\nQuality Assurance of DRC deck for Devices by SKILL Automation\n\nThe quality of the Process Design Kit (PDK) is crucial for the success of any System-on-Chip (SOC) for any organizati on. Design Rule check is one of the mandatory checks in the sign-off proce ss of a SOC or an IP. The QAcell methodology involves exhaustively creati ng small layouts representing the v...\n\n\nAmbika Bhardwaj, Chirag Agarwa l, Piyush Soni, and kancou traore (STMicroelectronics)\n------------------ ---\nMethodology to analyze and optimize SOC performance and cost using fu nction agnostic cycle accurate models\n\nBillions of MCUs drive integratio n of more number of CPUs, DMAs and variety of peripherals at relatively hi gher performance. While the low-end SOC level performance, throughput requ irements was seldom analyzed systematically, it is impractical to ignore t hese aspects in mid-end to high-end MCUs due ...\n\n\nAtul Lele, Anuvrat S rivastava, and Ajeet Singh (Texas Instruments (India) Pvt. Ltd.) and Ashut osh Mishra (Malaviya National Institute of Technology Jaipur)\n----------- ----------\nMemory Clusters – Divide the design and optimize MBIST inserti on efforts\n\nProblem Statement : Modern applications demand memory intens ive complex SOC's with tighter time to market schedules. For such designs; implementing high quality test and repair solution is a unique challenge to achieve with optimum mbist insertion efforts. Traditional MBIST inserti on methods needs m...\n\n\nSanthosh Ramappa (Marvell) and Subhash Baraiya (Marvell India Pvt. Ltd.)\n---------------------\nShift-left methodology t o identify invalid voltage level shifts & validate signal pins' P/G associ ation in IPs/Block's UPF & .LIB views using PERC's static-voltage tracing mechanism\n\nSeveral silicon failures were identified in NXP SOCs due to incorrect voltage level shifting caused either by incorrect Liberty/UPF v iews generated for the IPs or issues in design practices. Incorrectness in Liberty/UPF views propagates through the design and shields the detection of discrepancies ...\n\n\nSarvagya Tiwari (NXP Semiconductors), GAZAL SIN GLA (Siemens), and Shubham Sachdeva (NXP Semiconductors)\n---------------- -----\nCDC Simulation Checker Implementation for Constant and Quasi-static Data Paths\n\nIn the structural sign-off of metastability issues associat ed with Clock Domain Crossings (CDC), several assumptions are made, one of which is the presence of static signals. Static signals are typically cat egorized into two types: stable and constant. During the CDC structural si gn-off process, the...\n\n\nYoungchan Lee (Samsung)\n--------------------- \nEmpowering Early-Stage Design: An Automated Solution for Die Size Estima tion and IO Ring Creation\n\nIn the dynamic landscape of electronics desig n, the escalating market demand for new devices has led to increased compl exity in evaluating and comparing configurations and feature requirements based on customer needs and packages. This intricacy poses a challenge for designers, making decision-makin...\n\n\nGaurav Varshney (Texas Instrumen ts) and Dheeraj HA, Megha Naik, and MuraliMohan Thota (Texas Instruments ( India) Pvt. Ltd.)\n---------------------\nAdvanced LLE aware Timing Signof f Methodology\n\nThis presentation is about how to consider LLE impact in timing signoff flow. In advanced node, LLE impact is increased than before , so it has become an essential item to be considered.\nBecause this LLE i mpact could not be considered in timing signoff flow in the existing metho d, we introduce the ad...\n\n\nYoobeom Kim, Jingon Lee, Chul Rim, and Hyun seung Seo (Samsung) and Sangwoo Han, Ahmed Shebaita, Tajendra Singh, Li Di ng, and Sunik Heo (Synopsys)\n---------------------\nAreal and Time Decomp osed Phalanx based Dynamic IR-Drop Prediction using DNN(Deep Neural Networ k) at Earlier stage of Design cycle\n\nAs the semiconductor technology has been increased, a lot of challenges related to IR-Drop have been increase d considerably in recent years. Especially Dynamic IR-Drop issue becomes a bigger factor resulting in function failure and this will be true for adv anced process node below 5nm and smaller. W...\n\n\nSeihyung Jang, Gyusun Park, Kibum Kang, Yun Ra, Kisun Kim, Kisik Lee, Changsik Lee, and Hongsok Choi (SK hynix) and Taejin Kim, Hongpa Che, and Dongchul Kang (Cadence Des ign Systems, Inc.)\n---------------------\nPnr implementation challenges i n 3d ic\n\nTSVs creates repeated placement and route blockages in design.\ nSpecial care needed to deal with floorplan and power plan challenges to handle TSV.\nWith increase number of blockages and TSV islands, pre-place cell addition and power plan run time increases.\nModule splits near TSV, makes difficult f...\n\n\nArvind Kumar Mishra and choudhary Aditya Kumar (Samsung), Jeshwanth Rahul (FDS SSIR), and Sandeep Jadhav (Samsung)\n----- ----------------\nProgrammable IO Ring Builder and checker\n\nIO Ring is a key factor for any SoC Design. It consists of some specified cells which need to adhere to all the Integration Guidelines mentioned in the library databooks. Building an IO Ring is a bit challenging task for SoC designers . The designer needs to build the Ring manually with all required ...\n\n\ nManoj Kumar (Synopsys India Pvt. Ltd.) and Anurag Mittal, Praveen Jakki, Avinash Gupta, Priyanshi Jain, and Priyanka Goel (Synopsys)\n------------- --------\nCalibre Autowaiver for Early DRC & DFM Analysis In Big Die Desig ns\n\nWith the exponential growth in design complexity, stringent timeline s in Chip design cycle closure, the process advancements and increased run times in both physical design sign-off verification and Quality Analysis a re constantly driving the need for faster and more efficient physical veri fication (...\n\n\nVenkata Chinni (Samsung), Rahul Agarwal (Associate Staf f Engineer), and SRUTI L SHRIDHAR (Samsung)\n---------------------\nAutoma ted Place and Route based solution for Custom Blocks\n\nMost SoCs today ha ve analog or mixed signal blocks, such as SerDes cores, DACS, ADCs, PLLs a nd other transceivers. Many analog blocks have digital control logic. As s uch, an increasing amount of analog IP is mixed signal, and with rapidly i ncreasing SoC capacity, a single IP block might represent an...\n\n\nRajee v Singh and Atul Bhargava (STMicroelectronics); Akshita Bansal and Vishesh Kumar (Cadence Design Systems, Inc.); and Vijay Singh Khati (STMicroelect ronics)\n---------------------\nMethodology of linking the LDR and DRC cod e by automatically generated test pattern\n\nAs for the advancements in th e fabrication process, Integrated Circuits (ICs) blocks are complicatedly designed. One of the main verification method verifying the layout using D esign Rule Check (DRC) is commonly adopted. DRC is coded by the DRC team u nderstanding the intention of Layout Design Rule ...\n\n\nDongjin Kim, Kwo njae Kim, Seyeon Moon, Boyoung Lee, Youngwook Kim, and Jungyun Choi (Samsu ng)\n---------------------\nExecutable Tables, 'A Journey from Document to Simulation Capable, Exemplified Using DDR5 '\n\nThere has been an everlas ting trend to represent information in tabular form in any kind of documen t irrespective of the application since tabular format help convey more in formation in lesser words. But extracting and processing data from these t ables can be very challenging. Talking In context of ...\n\n\nRahil Jha an d Joseph Bauer (Cadence Design Systems, Inc.)\n---------------------\nTimi ng Closure Methods on 5nm Design Challenges\n\nHold timing violations can be challenging to fix especially with additional limitations in a 5nm desi gn that were not seen in larger nodes, such as power, crosstalk, and narro wer setup-hold window (less setup margin). Current Place and Route (PnR) a nd timing eco tools struggle to address these diffi...\n\n\nPatricia Fong (Marvell)\n---------------------\nElectromagnetic Solutions From Design to Sign-Off Stage For High-Speed SerDes Design\n\nIn high-speed SerDes desig n, to understand the EMag(electromagnetic) coupling between various elemen ts of a high-frequency semiconductor device is very important, these EMag interactions include not only the silicon chip but also extend to the pack age that encloses it. At sign-off phase, it is commo...\n\n\nYuhang Zhao, JinRong Yan, Hang Sun, and Xuewei Ding (Sanechips Technology Co.,Ltd) and Xiaomei You and Rodger Luo (Ansys)\n---------------------\nAI-Assisted Des ign Optimization for Extensive Design Spaces: Handling 260,000+ Combinatio ns\n\nThis presentation discusses how an AI-assisted design optimization m ethodology provides a verified optimal solution for two circuits: metal-op tion switches and charge pumps. By exploring the entire design space, up t o 260,000 design combinations in this case, it results in a faster design cycle, imp...\n\n\nAustin Rhodes (Micron) and Mohamed Atoua (Siemens)\n--- ------------------\nShift-left Solution for Enhancing Power Integrity in p hysical design construction with RedHawk-Fusion\n\n· With shrinking proces s node, dynamic voltage drop becomes an increasingly challenging issue, du e to the increased silicon frequency and reduced voltage headroom. \n· Adv ance tech nodes also have more resistive power grid (PG). Combination of P G complexity and design size increase is making designs ...\n\n\nKiran Adh ikari, Hailang Wang, Karthikk Sridharan, and Rossana Liu (Microsoft); Jin Wang (Synopsys); and Sreekanth R and Godwin Rajasekhar (Ansys)\n---------- -----------\nA Novel methodology for re-simulation of block vectors helpin g validate Power Optimization QoR 20x faster\n\nTo achieve the highest pow er savings, it is desired to make modification as early as possible in the design cycle requiring RTL Power Optimization flows. One of the major cha llenges with RTL Power Optimization is lack of eco-system to validate the impact on Power for the changes. To capture the powe...\n\n\nBhupesh Praja pat, Parul Dohare, Pratik Talekar, Manish Kumar, Divya Parihar, Sachin Kum ar, Mahima Jain, and Mohammed Fahad (Siemens)\n---------------------\nNove l Way of Checking and Analyzing Peak to Peak Voltage Variation Challenges for High Computational Multiprocessors SOC\n\nIncreasing functionality of Automotive multiprocessor SOCs has resulted in increasing power grid compl exity leading to high voltage-ripple noise caused by simultaneous switchin g of multiple processor blocks in the SoC. Meeting chip-package-system (CP S) performance targets becomes daunting due to thi...\n\n\nAmit Singh, Gov ind Pal, and Anil Yadav (STMicroelectronics) and Amit Jangra and Koshy Joh n (Ansys)\n---------------------\nA Single Source Unified Approach to CSR Register Development\n\nThe semiconductor industry faces a significantly h igher portion of third-party IP, and the number of Status and Control Regi sters (CSRs) can now grow to 5M+. Hardware/software interfaces (HSIs) are critical, and users write and maintain homegrown scripts and solutions and spend significant manual ef...\n\n\nInsaf Meliane, Andy Nightingale, and Rich Weber (Arteris)\n---------------------\nMemory Interface Architecture s for Test Time Reduction in Zero DPPM SoCs\n\nThe semiconductor manufactu ring process is far from perfect; therefore, testing is required to distin guish between functionally correct devices and devices that are defective due to production abnormalities. As the number of transistors on a die inc reases and more dies are added onto a board or into...\n\n\nNitesh Mishra and Hrithik Sahni (Texas Instruments)\n---------------------\nDesign Enabl ement of 2D/3D Power-Thermal Self-Consistent Analysis\n\nIn the last years , CMOS scaling becomes slower than used to be and it becomes more challeng ing to follow Moore's law. One of the proposed scaling boosters is system level 3D-IC where the vertical dimension is used by stacking dies on top o f each other. Fine-pitch 3D interconnects such as wafer-to-wa...\n\n\nMoha med Naeim and Yun Dai (Cadence Design Systems, Inc.) and Dwaipayan Biswas and Dragomir Milojevic (imec)\n---------------------\nA Novel Approach to Cost-Efficient Hybrid Cloud Solutions with SeaScape's Data Lake and Micro- Resiliency\n\narm has always been exploring the cloud advantages and is qu ite motivated to be fully Cloud enabled. On cloud, spot instances have alw ays been the cost effective solution but not many EDA tools can leverage t his advantage. Spot instances offer a cost-effective solution by taking ad vantage of unused ...\n\n\nMohit Srivastava and Ajay Chopra (Arm Ltd.) and Naveen B, Sankar Ramachandran, Sooraj JP, and Vyom Garg (Ansys)\n-------- -------------\nCOBRA : Code Coverage Measurement Technique for ARM-based f irmware using Binary Modification Technology\n\nThere are limitations to m easuring code coverage during runtime in ARM Architecture-based firmware, such as (1) limitations in available memory and (2) multi-core system.\nIn this paper, we propose and apply a new technique using Binary Modificatio n technology to measure code coverage for ARM Archite...\n\n\nwonchol kim (Samsung)\n---------------------\nBalancing Power and Performance: The Hyb rid Clock Network Approach for Network on chips\n\nIn the rapidly evolving landscape of technology, the pursuit of high-performance systems has beco me increasingly essential. With the growing complexities in chip design, a chieving a harmonious balance between Power, Performance, and Area (PPA) – the foundational pillars of contemporary chip architec...\n\n\nPallapu La kshmi Sarvaani (Indian Institute of Technology, Tirupati) and Subba Annapa lli and Ponnada Appala Naidu (Intel Technology India. Pvt. Ltd)\n--------- ------------\nRapid Retargeting of Formal Connectivity Verification of AI FPGA Systems\n\nOur objective is to exhaustively verify static and dynamic connections, from the IPs deep inside an FPGA "core," all the way t the o uter perimeter of an AI-centric computational circuit boards. The circuits usually have FPGAs from different vendors, many configurations, pinouts, implementation const...\n\n\nLinh Nguyen, Benjamin Ting, and Nguyen Le (Mi crosoft) and Jin Hou, Rahul Seth, and Sasa Stamenkovic (Siemens)\n-------- -------------\nDesign Closure Methodology using stage wise checkers by Eas e of Review to minimize Physical Design Implementation & Closure TAT\n\nAn efficient and effective methodology for an overall turn around time reduc tion during physical design implementation phase of SOC Design. This has b een implemented via automated stagewise checkers and ease of review dashbo ard. The smooth and ease of project execution involves data gathering duri ng...\n\n\nShilpi Srivastava, Daniel Hand, and Jagadeesh Gnanasekaran (Int el Technologies India Private Ltd)\n---------------------\nGlobalized bulk biasing based substrate noise reducing method for size reduction in digit al circuit\n\nTechnology scaling results in smaller die size with increase d amount of bulk-biasing penalty. In this paper, we propose a physical syn thesis methodology for digital circuit that minimizes the overhead. Consid ering bulk-biasing constraint of mutual distance and density, we first pla ce global bulk-bia...\n\n\nChangyeon Yu, Ahreum Kim, Pansuk Kwak, and Dong ku Kang (Samsung)\n---------------------\nEarly Clock Tree Power Estimatio n and Correlation at SoC: A Case Study\n\nClock trees significantly contri bute to the overall power consumption of a design, accounting for approxim ately 30-40% of the total power. Effectively estimating and analyzing cloc k power at the System-on-Chip (SoC) level is crucial for identifying and o ptimizing weak areas in the design. The identi...\n\n\nSri Sai Pavan Pasum arthi, Sudheer Yadapalli, and Vineet Ooramkumarath (Qualcomm)\n----------- ----------\nA Closed Loop IR and Timing Comprehensive Co-Signoff Methodolo gy\n\nTraditionally, the budgeting of STA and IR drop limits was done sepa rately, with each converging to their respective limits without much inter action. Recently, there have been attempts to incorporate IR drop into STA analysis for a more informed timing signoff. However, the reverse - incor porating t...\n\n\nOnkar Hule, Rossana Liu, Medha Kulkarni, Hailang Wang, Amit Garg, and Pranav Ranganathan (Microsoft) and Sreekanth Rajan and Amit Jangra (Ansys)\n---------------------\nEnhanced State-Propagation based V ectorless IR-Drop Analysis Emulating Realistic Silicon Behavior\n\nPre-Sil icon IR-drop analysis accuracy depends on the logic toggling scenarios cov ered, along with other factors. Vector-based IR drop analysis is more accu rate as real stimuli are used, but generally cannot cover the whole design or toggling scenarios, hence vectorless analysis is conventionally use... \n\n\nSubhadeep Ghosh and Rishabh Singh (Texas Instruments); Ruchin Gupta and Sushant Sharma (Cadence Design Systems, Inc.); and Gaurav Kumar Varshn ey (Texas Instruments)\n---------------------\nPredicting Computer Resourc e Needs using Machine Learning and Conventional Design\n\nToday, the semic onductor design industry is centered around the use of EDA tools. These to ols provide the necessary information and automation for a design engineer to do their work effectively. The automation of design processes is espec ially significant and has been key to the success of the indus...\n\n\nJus tin Conklin (Marvell)\n---------------------\nAchieving High Local Noise C overage in Dynamic EMIR Analysis using SigmaDVD\n\nAutomotive-grade multip rocessor System-on-Chips (SoCs) operating in advanced FinFET nodes demand unparalleled reliability and quality. Ensuring power integrity signoff for these SoCs is crucial, necessitating extensive coverage of local switchin g noise for EMIR analyses. Conventional vectorless EMIR...\n\n\nGovind Pal (STMicroelectronics) and Amit Jangra and Koshy John (Ansys)\n------------ ---------\nA Novel Methodology for Library Characterization and Modeling C onsidering Local Layout Effect\n\nLLE (Local Layout Effect) refers to the mutual influence of adjacent layout elements in semiconductor design. In t he process of measuring the characteristics of standard cells, LLE context assumptions are stored in design kit together to be utilized for the bloc k level analysis.To minimize LLE impac...\n\n\nYoobeom Kim, Hyunseung Seo, CheolJun Bae, Jingon Lee, and Chul Rim (Samsung) and Edson Gomersall, Ram esh Kamath, Shupeng Cui, and Mehar Gupta (Cadence Design Systems, Inc.)\n- --------------------\nDesign Automation of Minimal Layer Count Microproces sor 2.5D Silicon Interposer\n\nIntel latest microprocessors are built by c hiplet assembly over Foveros passive silicon interposer. Second generation based on this technology was targeting a more aggressive cost optimizatio n, featuring reduced interposer layer count and decoupling density. Strong er design automation flows were dev...\n\n\nOmer Vikinski, Basil Tarabiea, and Alexander Waizman (Intel Corporation)\n---------------------\nNoise F ixup: Finding and Fixing Noise Problems ( Chop and Swap )\n\nChop and Swap methodology was architected for noise mitigation that saved\nmultiple des igners weeks of manual chip integration work in a project.\nWhen a noise e vent happens, the closer the aggressor and victim wires are, the\nmore noi se coupling occurs, causing NIOT (Noise Impact on Timing) or NIOF\n(N...\n \n\nAdam Matheny (IBM)\n---------------------\nA Decade of Evolution in Fo rmal Verification\n\nNearly a decade ago, in July 2015, we released the 1s t edition of our book "Formal Verification: An Essential Toolkit for Mode rn VLSI Design". This book was well-received in the industry, being esse ntially the first practical modern guidebook on the topic of Formal Verifi cation (FV) aimed at acti...\n\n\nErik Seligman (Cadence Design Systems, I nc.) and M V Kiran Kumar (Intel Corporation)\n---------------------\nMicro soft's Comprehensive IP Handoff Flow\n\nMicrosoft addresses diverse IP cha llenges by prioritizing quality control for internal design teams, resolvi ng handoff complexities, and managing 3rd party IPs with format inconsiste ncies. They emphasize early quality checks in design, acknowledging the ri sing cost of addressing IP issues later in t...\n\n\nMartin Sanchez (Micro soft) and Siddharth Ravikumar and Mary Rayburn (Siemens)\n---------------- -----\nRedefining Hierarchical Power Integrity signoff for Ultra-Large Sys tem-on-Chips\n\nModern SoCs, with billions of transistors, pose challenges for traditional power integrity signoff due to increased node counts and process scaling. The existing methods are time-consuming, require substant ial resources, and often result in systematic inaccuracies. To address thi s, a bottom-up hiera...\n\n\nPiyush Jain, Rossana Liu, Hailang Wang, Apurv a Soni, Medha Kulkarni, and Pranav Ranganathan (Microsoft) and Chidambaram Rakkappan, Amit Jangra, Godwin Rajasekhar, and Sreekanth Rajan (Ansys)\n- --------------------\nOvercoming Collaboration Hurdles in High-Tech Produc t Development with Keysight tool on Azure infrastructure.\n\nThe intricate dance of high-tech product development demands seamless synchronization a mong partners. Miscommunication and data silos threaten deadlines, costs, and, ultimately, product quality. This abstract presents a solution to bri dge these collaboration gaps. Current challenges in cross-company...\n\n\n Amit Varde (Keysight Technologies) and Joe Tostenrude (Microsoft)\n------- --------------\nSigmaDVD: High Coverage Solution for Power Integrity Signo ff\n\nSigmaDVD is a unique simulation method that provides complete power grid noise coverage for 100% of the design instances. This novel simulatio n technique generates tens of thousands of unique, physically and timing r elevant switching scenarios for each instance independently, finding the s tatistical...\n\n\nAnusha Vemuri, Emmanuel Chao, and Santosh Santosh (NVID IA) and Chidambaram Rakkappan and Ed Deeters (Ansys)\n-------------------- -\nDeveloping Software Test Library (STL) as a Safety Mechanism for Vision AI DSP\n\nCeva SensPro AI & Vision DSP are embedded within automotive and many other markets' chips that require safety. Showing that DSP matches t he safety metrics set by ISO 26262 for relevant ASIL is critical across th ese markets as they move towards having advanced ADAS and autonomous drivi ng solutions. S...\n\n\nNoam Meser and Zvika Melamed (Ceva Technologies, L td.) and Sesha Sai Kumar C V, Ayman Mouallem, and Fares Jaraisy (Optima De sign Automation Ltd)\n---------------------\nSmart Testing: Integrating Fa ult Simulation and AI/ML for Efficient IP Validation\n\nIn this innovative approach to IP validation, we address growing complexity of designs by in tegrating advanced Fault Simulation (FS) and Artificial Intelligence/Machi ne Learning (AI/ML) techniques. Traditionally, validating (I/O) in complex IP designs required extensive test vectors, leading prolong...\n\n\nHiman shu Vishwakarma, Priyanka Gharat, and Gopi Srinivas Deepala (Silicon Inter faces)\n---------------------\n2.5D Design Breakthrough: Unleashing the Po wer of Automated EMIB Bridges.\n\nWith the growing demand for the heteroge nous chip interconnect there is a dire need of a unified EDA design enviro nment that effectively handles the complex logical interconnects, physical layout design, EE, mechanical & thermal simulations.\nIntel's embedded mu lti-die interconnect bridge (EMIB) is a...\n\n\nSam Mirza (Intel Corporati on)\n---------------------\nStruct Based Lower Level Modelling Using Syste mVerilog UDT for Verification of Power Management IC\n\nIn this presentati on, we introduce typical challenges encountered in the Digital Mixed-Signa l (DMS) verification of a Power Management Integrated Circuit (PMIC), when its blocks are modelled in real number using High-Level Modelling (HLM) m ethodology. We talk about the traditional approach for mode...\n\n\nVijay Kumar, Keerthana K, and Celeste Anil Lagali (Samsung)\n------------------ ---\nDie-Level Dynamic-IR Analysis Shift-Left Enabled by RedHawk-SC SigmaD VD\n\nAs Silicon scaling continue to reach into Angstrom domain, dimension scaling slows down. however silicon feature and compute power stills cont inue to increase at rate comparable to Moore's Law. Power Integrity is now becoming a key challenge for sub nanometer processes. Die-level Power Int egrity sig...\n\n\nRuiqi Wu (UNISOC); Ran Zhang, Luca Cui, and Chang Zhao (Ansys); and Marc Zheng (UNISOC)\n---------------------\nMachine-Learning- Driven Floorplan-Aware Power Delivery Network Co-Planning\n\nEnabling new applications such as autonomous driving or car architectures with centrali zed ECUs, heterogeneous systems-on-chip (SoCs) with multiple CPUs, multi-l evel memory hierarchies, various co-processors and hardware accelerators i s becoming a key architectural paradigm. Such highly dense automo...\n\n\n Bogdan Tabacaru (Infineon Technologies) and Jerome Toublanc (Ansys)\n----- ----------------\nOn Cloud Secured Collaboration From chips to embedded sy stems\n\nAbstract :\n\nThe need for a secured collaboration arises from th e imperative to protect sensitive information and ensure the integrity of shared data. In order to face strong industrial constraints, industry play ers must ensure that communication between the different links in their va lue chain is fl...\n\n\nSmriti Joshi and Manuel Rei (Dassault Systèmes)\n\ nTopic: Back-End Design, Embedded Systems, Front-End Design, IP END:VEVENT END:VCALENDAR