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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess232_ETPOST001@linklings.com
SUMMARY:A Decade of Evolution in Formal Verification
DESCRIPTION:Engineering Track Poster\n\nErik Seligman (Cadence Design Syst
 ems, Inc.) and M V Kiran Kumar (Intel Corporation)\n\nNearly a decade ago,
  in July 2015, we released the 1st edition of our book "Formal Verificatio
 n:  An Essential Toolkit for Modern VLSI Design".   This book was well-rec
 eived in the industry, being essentially the first practical modern guideb
 ook on the topic of Formal Verification (FV) aimed at active engineers des
 igning and validating RTL models, rather than theoretical researchers.   H
 owever, we are part of a rapidly evolving field, and our notion of best pr
 actices for FV has undergone many changes in the years since the initial r
 elease.   We have also gained a variety of different experiences— while al
 l three authors had worked together at Intel when beginning the first edit
 ion, since then one author moved to academia, and another moved from Intel
  to EDA vendor Cadence.    It is the gradual accumulation of these changes
  and varied new learnings that eventually motivated us to put out a heavil
 y revised 2nd edition, released in June 2023.   Since not every FV practit
 ioner has purchased our 2nd edition, or has kept completely up-to-date wit
 h FV methodology at other companies in the industry, we think it will be u
 seful to summarize some of the major areas in which FV practice has change
 d and improved in the years leading up to our 2nd edition.   This informat
 ion will help current designers, validators, and FV specialists to improve
  their practices and enable them to better incorporate the industry's late
 st learnings.\n\nTopic: Back-End Design, Embedded Systems, Front-End Desig
 n, IP
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