BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180035Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST019@linklings.com
SUMMARY:Globalized bulk biasing based substrate noise reducing method for 
 size reduction in digital circuit
DESCRIPTION:Engineering Track Poster\n\nChangyeon Yu, Ahreum Kim, Pansuk K
 wak, and Dongku Kang (Samsung)\n\nTechnology scaling results in smaller di
 e size with increased amount of bulk-biasing penalty. In this paper, we pr
 opose a physical synthesis methodology for digital circuit that minimizes 
 the overhead. Considering bulk-biasing constraint of mutual distance and d
 ensity, we first place global bulk-biasing active before standard cell pla
 cement. Then, to guarantee the biasing constraints, we transform the place
 ment using slide-window algorithm. For 3D V-NAND digital design [1], measu
 rement result showed 7.2% of area reduction compared to the conventional m
 ethodology.\n\n[1]         M. Kim et al., "A 1Tb 3b/Cell 8th-Generation 3D
 -NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface,"
  ISSCC 2022:136-137.\n\nTopic: Back-End Design, Embedded Systems, Front-En
 d Design, IP
END:VEVENT
END:VCALENDAR