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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST029@linklings.com
SUMMARY:Rapid Retargeting of Formal Connectivity Verification of AI FPGA S
 ystems
DESCRIPTION:Engineering Track Poster\n\nLinh Nguyen, Benjamin Ting, and Ng
 uyen Le (Microsoft) and Jin Hou, Rahul Seth, and Sasa Stamenkovic (Siemens
 )\n\nOur objective is to exhaustively verify static and dynamic connection
 s, from the IPs deep inside an FPGA "core," all the way t the outer perime
 ter of an AI-centric computational circuit boards. The circuits usually ha
 ve FPGAs from different vendors, many configurations, pinouts, implementat
 ion constraints which lead to high risk of connection bugs.\n\nThe simulat
 ion approach is not working for our multiple variants of large-scale, comp
 lex FPGA-based, AI-centric cloud hardware designs to meet our tight schedu
 le, since it requires weeks of manual testbench development, weeks of run 
 and turnaround time, and it is not exhaustive, and bugs can escape.\n\nFor
 mal connectivity verification establishes a framework for both experts and
  non-experts alike that ensures simplicity, reusability, and scalability, 
 from block-to-system level, static and dynamic connectivity verification. 
 It provides a comprehensive exposition of the design hierarchies required 
 by backend physical tools, provides visibility into hidden cone of logic u
 ncovering "blind spots" that escape detection in simulation-based techniqu
 es, and exhaustively proves connections when no stimulus can violate them.
 \n\nWith formal verification, we successfully uncovered RTL bugs in minute
 s - a task that weeks of simulation-based regressions had failed to accomp
 lish. We got huge boost in productivity - 95% savings in engineer's time!\
 n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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