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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST042@linklings.com
SUMMARY:Methodology to analyze and optimize SOC performance and cost using
  function agnostic cycle accurate models
DESCRIPTION:Engineering Track Poster\n\nAtul Lele, Anuvrat Srivastava, and
  Ajeet Singh (Texas Instruments (India) Pvt. Ltd.) and Ashutosh Mishra (Ma
 laviya National Institute of Technology Jaipur)\n\nBillions of MCUs drive 
 integration of more number of CPUs, DMAs and variety of peripherals at rel
 atively higher performance. While the low-end SOC level performance, throu
 ghput requirements was seldom analyzed systematically, it is impractical t
 o ignore these aspects in mid-end to high-end MCUs due to complexity of in
 tegration and performance requirements.  \nWe present methodology to addre
 ss the mentioned problem \n- Peripheral model managing internal FIFO reads
 /writes agnostic of its function of communication/conversion/processing\n-
  System DMA model with customization options to take care of channel prior
 ity, channel switching and R/W transfer latency \n- Determine throughput a
 t SOC level using above models by running dynamic simulation as per SOC sp
 ecification \n- Optimize internal memory/buffer/FIFO sizes according to mo
 del performance which in turn helps to save cost OR \n- Analyze possible p
 erformance trade-offs for various scenarios with existing buffer/FIFO size
 s and clock frequency of operation \n\nIn this presentation, we focus on f
 ollowing method - \nHolistic simulation environment using cycle accurate C
 /SystemC models primarily supporting code execution by cycle accurate ARM 
 CPU models. This is scalable to include/exclude other models as per SOC co
 nfiguration, change peripheral and SOC configuration on need basis, more i
 mportantly, evaluate architecture trade-offs very early at the design expl
 oration stage\n\nTopic: Back-End Design, Embedded Systems, Front-End Desig
 n, IP
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